#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#

if ARCH_CHIP_STM32H5

comment "STM32H5 Configuration Options"

choice
	prompt "STM32 H5 Chip Selection"
	default ARCH_CHIP_STM32H563ZI
	depends on ARCH_CHIP_STM32H5

config ARCH_CHIP_STM32H563ZI
	bool "STM32H563ZI"
	select ARCH_CORTEXM33
	select STM32H5_STM32H5XXXX
	select STM32H5_STM32H56XXX
	select STM32H5_STM32H563XX
	select STM32H5_STM32H5X3XX
	select STM32H5_FLASH_CONFIG_I
	select STM32H5_IO_CONFIG_Z
	---help---
		STM32 H5 Cortex M33, 512 Kb FLASH, 256 Kb SRAM

endchoice # STM32 H5 Chip Selection

# Chip families:

config STM32H5_STM32H5XXXX
	bool
	default n
	select ARCH_HAVE_FPU
	select STM32H5_HAVE_ICACHE

config STM32H5_STM32H56XXX
	bool
	default n
	select STM32H5_HAVE_FDCAN1
	select STM32H5_HAVE_FDCAN2
	select STM32H5_HAVE_LPUART1
	select STM32H5_HAVE_USART1
	select STM32H5_HAVE_USART2
	select STM32H5_HAVE_USART3
	select STM32H5_HAVE_UART4
	select STM32H5_HAVE_UART5
	select STM32H5_HAVE_USART6
	select STM32H5_HAVE_UART7
	select STM32H5_HAVE_UART8
	select STM32H5_HAVE_UART9
	select STM32H5_HAVE_USART10
	select STM32H5_HAVE_USART11
	select STM32H5_HAVE_UART12
	select STM32H5_HAVE_SPI4
	select STM32H5_HAVE_SPI5
	select STM32H5_HAVE_SPI6
	select STM32H5_HAVE_I2C4
	select STM32H5_HAVE_USBFS
	select STM32H5_HAVE_HSI48
	select STM32H5_HAVE_ICACHE_REMAP

config STM32H5_STM32H563XX
	# STM32H552 and STM32H562 devices documented in RM0439
	bool
	default n
	select STM32H5_HAVE_ETHERNET

choice
	prompt "Override Flash Size Designator"
	depends on ARCH_CHIP_STM32H5
	default STM32H5_FLASH_OVERRIDE_DEFAULT
	---help---
		STM32H5 series parts numbering (sans the package type) ends with a letter
		that designates the FLASH size.

			Designator  Size in KiB
				 8          64
				 B         128
				 C         256
				 E         512
				 G        1024
				 I        2048

		This configuration option defaults to using the configuration based on that designator
		or the default smaller size if there is no last character designator is present in the
		STM32 Chip Selection.

		Examples:
		   If the STM32H576VE is chosen, the Flash configuration would be 'E', if a variant of
		   the part with a 1024 KiB Flash is released in the future one could simply select
		   the 'G' designator here.

		   If an STM32H5xxx Series parts is chosen the default Flash configuration will be set
		   herein and can be changed.

config STM32H5_FLASH_OVERRIDE_DEFAULT
	bool "Default"

config STM32H5_FLASH_OVERRIDE_8
	bool "8 64 KB"

config STM32H5_FLASH_OVERRIDE_B
	bool "B 128 KB"

config STM32H5_FLASH_OVERRIDE_C
	bool "C 256 KB"

config STM32H5_FLASH_OVERRIDE_E
	bool "E 512 KB"

config STM32H5_FLASH_OVERRIDE_G
	bool "G 1024 KB"

config STM32H5_FLASH_OVERRIDE_I
	bool "I 2048 KB"

endchoice # "Override Flash Size Designator"

# Flash configurations

config STM32H5_FLASH_CONFIG_B
	bool
	default n
	depends on STM32H5_STM32H50XXX

config STM32H5_FLASH_CONFIG_C
	bool
	default n
	depends on STM32H5_STM32H52XXX

config STM32H5_FLASH_CONFIG_E
	bool
	default n
	depends on STM32H5_STM32H52XXX || STM32H5_STM32H53XXX

config STM32H5_FLASH_CONFIG_G
	bool
	default n
	depends on STM32H5_STM32H56XXX

config STM32H5_FLASH_CONFIG_I
	bool
	default n
	depends on STM32H5_STM32H56XXX || STM32H5_STM32H57XXX

# Pin/package configurations

config STM32H5_IO_CONFIG_K
	bool
	default n

config STM32H5_IO_CONFIG_T
	bool
	default n

config STM32H5_IO_CONFIG_C
	bool
	default n

config STM32H5_IO_CONFIG_R
	bool
	default n

config STM32H5_IO_CONFIG_J
	bool
	default n

config STM32H5_IO_CONFIG_M
	bool
	default n

config STM32H5_IO_CONFIG_V
	bool
	default n

config STM32H5_IO_CONFIG_Q
	bool
	default n

config STM32H5_IO_CONFIG_Z
	bool
	default n

config STM32H5_IO_CONFIG_A
	bool
	default n

comment "STM32H5 SRAM2 Options"

config STM32H5_SRAM2_HEAP
	bool "SRAM2 is used for heap"
	default n
	select STM32H5_SRAM2_INIT

config STM32H5_SRAM2_INIT
	bool "SRAM2 is initialized to zero"
	default n
	---help---
		If the SRAM2 is being used for it's battery-backed capability,
		this may be undesirable (because it will destroy the contents).  In that
		case, the board should handle the initialization itself at the appropriate
		time.

config STM32H5_PROGMEM
	bool "Flash progmem support"
	default n
	---help---
		Add progmem support, start block and end block options are provided to
		obtain a uniform flash memory mapping.

comment "STM32H5 Peripherals"

menu "STM32H5 Peripheral Selection"

# These "hidden" settings determine if a peripheral option is available
# for the selected MCU

config STM32H5_HAVE_ETHERNET
	bool
	default n

config STM32H5_HAVE_PHY_POLLED
	bool
	default n

config STM32H5_HAVE_FDCAN1
	bool
	default n

config STM32H5_HAVE_FDCAN2
	bool
	default n

config STM32H5_HAVE_HSI48
	bool
	default n

config STM32H5_HAVE_ICACHE
	bool
	default n

config STM32H5_HAVE_I2C4
	bool
	default n

config STM32H5_HAVE_LPUART1
	bool
	default n

config STM32H5_HAVE_SPI5
	bool
	default n

config STM32H5_HAVE_SPI6
	bool
	default n

config STM32H5_HAVE_USART1
	bool
	default n

config STM32H5_HAVE_USART2
	bool
	default n

config STM32H5_HAVE_USART3
	bool
	default n

config STM32H5_HAVE_UART4
	bool
	default n

config STM32H5_HAVE_UART5
	bool
	default n

config STM32H5_HAVE_USART6
	bool
	default n

config STM32H5_HAVE_UART7
	bool
	default n

config STM32H5_HAVE_UART8
	bool
	default n

config STM32H5_HAVE_UART9
	bool
	default n

config STM32H5_HAVE_USART10
	bool
	default n

config STM32H5_HAVE_USART11
	bool
	default n

config STM32H5_HAVE_UART12
	bool
	default n

config STM32H5_HAVE_USBFS
	bool
	default n

# These "hidden" settings are the OR of individual peripheral selections
# indicating that the general capability is required.

config STM32H5_ADC
	bool
	default n

config STM32H5_DMA
	bool
	default n

config STM32H5_FDCAN
	bool
	default n

config STM32H5_SPI
	bool
	default n

config STM32H5_SPI_DMA
	bool
	default n

config STM32H5_TIM
	bool
	default n

config STM32H5_USART
	bool
	default n

# These are the peripheral selections proper

config STM32H5_ADC1
	bool "ADC1"
	default n
	select STM32H5_ADC

config STM32H5_ADC2
	bool "ADC2"
	default n
	select STM32H5_ADC

config STM32H5_DMA1
	bool "DMA1"
	default n
	select STM32H5_DMA
	select ARCH_DMA

config STM32H5_DMA2
	bool "DMA2"
	default n
	select STM32H5_DMA
	select ARCH_DMA

config STM32H5_DTS
	bool "DTS"
	default n
	---help---
		Enable support for the on‑die digital temperature sensor (DTS)
		built into STM32H5 devices.  When enabled, the driver will register
		a `/dev/sensor_tempX` device using the common NuttX sensor framework.

config STM32H5_ETHMAC
	bool "Ethernet MAC"
	default n
	depends on STM32H5_HAVE_ETHERNET
	select NETDEVICES
	select ARCH_HAVE_PHY
	select STM32H5_HAVE_PHY_POLLED

config STM32H5_FDCAN1
	bool "FDCAN1"
	default n
	depends on STM32H5_HAVE_FDCAN1
	select STM32H5_FDCAN

config STM32H5_FDCAN2
	bool "FDCAN2"
	default n
	depends on STM32H5_HAVE_FDCAN2
	select STM32H5_FDCAN

config STM32H5_ICACHE
	bool "ICACHE"
	default n
	depends on STM32H5_HAVE_ICACHE

config STM32H5_QSPI1
	bool "QSPI1"
	default n

menu "U[S]ART/LPUART Selection"

config STM32H5_UART4
	bool "UART4"
	default n
	depends on STM32H5_HAVE_UART4
	select ARCH_HAVE_SERIAL_TERMIOS
	select STM32H5_USART

config STM32H5_UART5
	bool "UART5"
	default n
	depends on STM32H5_HAVE_UART5
	select ARCH_HAVE_SERIAL_TERMIOS
	select STM32H5_USART

config STM32H5_UART7
	bool "UART7"
	default n
	depends on STM32H5_HAVE_UART7
	select ARCH_HAVE_SERIAL_TERMIOS
	select STM32H5_USART

config STM32H5_UART8
	bool "UART8"
	default n
	depends on STM32H5_HAVE_UART8
	select ARCH_HAVE_SERIAL_TERMIOS
	select STM32H5_USART

config STM32H5_UART9
	bool "UART9"
	default n
	depends on STM32H5_HAVE_UART9
	select ARCH_HAVE_SERIAL_TERMIOS
	select STM32H5_USART

config STM32H5_UART12
	bool "UART12"
	default n
	depends on STM32H5_HAVE_UART12
	select ARCH_HAVE_SERIAL_TERMIOS
	select STM32H5_USART

config STM32H5_USART1
	bool "USART1"
	default n
	depends on STM32H5_HAVE_USART1
	select ARCH_HAVE_SERIAL_TERMIOS
	select STM32H5_USART

config STM32H5_USART2
	bool "USART2"
	default n
	depends on STM32H5_HAVE_USART2
	select ARCH_HAVE_SERIAL_TERMIOS
	select STM32H5_USART

config STM32H5_USART3
	bool "USART3"
	default n
	depends on STM32H5_HAVE_USART3
	select ARCH_HAVE_SERIAL_TERMIOS
	select STM32H5_USART

config STM32H5_USART6
	bool "USART6"
	default n
	depends on STM32H5_HAVE_USART6
	select ARCH_HAVE_SERIAL_TERMIOS
	select STM32H5_USART

config STM32H5_USART10
	bool "USART10"
	default n
	depends on STM32H5_HAVE_USART10
	select ARCH_HAVE_SERIAL_TERMIOS
	select STM32H5_USART

config STM32H5_USART11
	bool "USART11"
	default n
	depends on STM32H5_HAVE_USART11
	select ARCH_HAVE_SERIAL_TERMIOS
	select STM32H5_USART

config STM32H5_LPUART1
	bool "LPUART1"
	default n
	depends on STM32H5_HAVE_LPUART1
	select ARCH_HAVE_SERIAL_TERMIOS
	select STM32H5_USART

endmenu # U[S]ART/LPUART Selection

menu "I2C Selection"

config STM32H5_I2C
	bool
	default n

config STM32H5_I2C1
	bool "I2C1"
	default n
	select STM32H5_I2C

config STM32H5_I2C2
	bool "I2C2"
	default n
	select STM32H5_I2C

config STM32H5_I2C3
	bool "I2C3"
	default n
	select STM32H5_I2C

config STM32H5_I2C4
	bool "I2C4"
	default n
	depends on STM32H5_HAVE_I2C4
	select STM32H5_I2C

endmenu # I2C Selection

menu "SPI Selection"

config STM32H5_SPI1
	bool "SPI1"
	default n
	select SPI
	select STM32H5_SPI

config STM32H5_SPI2
	bool "SPI2"
	default n
	select SPI
	select STM32H5_SPI

config STM32H5_SPI3
	bool "SPI3"
	default n
	select SPI
	select STM32H5_SPI

config STM32H5_SPI4
	bool "SPI4"
	default n
	depends on STM32H5_HAVE_SPI4
	select SPI
	select STM32H5_SPI

config STM32H5_SPI5
	bool "SPI5"
	default n
	depends on STM32H5_HAVE_SPI5
	select SPI
	select STM32H5_SPI

config STM32H5_SPI6
	bool "SPI6"
	default n
	depends on STM32H5_HAVE_SPI6
	select SPI
	select STM32H5_SPI

endmenu # SPI Selection

menu "STM32H5 Timer Selection"

config STM32H5_TIM1
	bool "TIM1"
	default n
	select STM32H5_TIM

config STM32H5_TIM2
	bool "TIM2"
	default n
	select STM32H5_TIM

config STM32H5_TIM3
	bool "TIM3"
	default n
	select STM32H5_TIM

config STM32H5_TIM4
	bool "TIM4"
	default n
	select STM32H5_TIM

config STM32H5_TIM5
	bool "TIM5"
	default n
	select STM32H5_TIM

config STM32H5_TIM6
	bool "TIM6"
	default n
	select STM32H5_TIM

config STM32H5_TIM7
	bool "TIM7"
	default n
	select STM32H5_TIM

config STM32H5_TIM8
	bool "TIM8"
	default n
	select STM32H5_TIM

config STM32H5_TIM12
	bool "TIM12"
	default n
	select STM32H5_TIM

config STM32H5_TIM13
	bool "TIM13"
	default n
	select STM32H5_TIM

config STM32H5_TIM14
	bool "TIM14"
	default n
	select STM32H5_TIM

config STM32H5_TIM15
	bool "TIM15"
	default n
	select STM32H5_TIM

config STM32H5_TIM16
	bool "TIM16"
	default n
	select STM32H5_TIM

config STM32H5_TIM17
	bool "TIM17"
	default n
	select STM32H5_TIM

endmenu # STM32H5 Timer Selection

config STM32H5_USBFS
	bool "USB Device"
	default n
	depends on STM32H5_HAVE_USBFS
	select USBDEV

endmenu # STM32H5 Peripheral Selection

menu "DTS Configuration"
	depends on STM32H5_DTS

config STM32H5_DTS_REFCLK_LSE
	bool "Use LSE (32.768 kHz crystal) as DTS reference clock"
	default n
	---help---
		Select the low‑speed external (LSE) oscillator as the reference clock
		for the DTS.  When enabled, DTS_CFGR1.REFCLK_SEL=1 and the driver will
		measure FM(T) pulses over N LSE cycles.

		If disabled, the DTS will use the APB‑bus clock (PCLK) as the reference
		(REFCLK_SEL=0) and you must supply a valid HSREF_CLK_DIV to keep the
		calibration prescaler ≤ 1 MHz.

config STM32H5_DTS_SMP_TIME
	int "DTS sampling time (TS1_SMP_TIME[3:0])"
	default 1
	range 1 15
	---help---
		Number of reference‑clock cycles (PCLK or LSE) counted per
		DTS measurement.  Valid range 1 (1 cycle) through 15 (15 cycles).

config STM32H5_DTS_TRIGGER
	int "DTS hardware trigger source (TS1_INTRIG_SEL[3:0])"
	default 0
	---help---
		If non‑zero, DTS will start measurements on the rising edge of
		the selected hardware line.  Values match RM0481 Table 275:
		0=Software Trigger, 1=LPTIM1_CH1, 
		2=LPTIM2_CH1, 3=LPTIM3_CH1, 4=EXTI13, 5-15 are reserved.

config STM32H5_DTS_LOW_THRESHOLD
	int "DTS low‑threshold (°C)"
	default 0
	---help---
		The temperature (in whole °C) below which the DTS window comparator will
		assert the low‑threshold flag (TS1_ITLF).  To disable, set equal to 0.

config STM32H5_DTS_HIGH_THRESHOLD
	int "DTS high‑threshold (°C)"
	default 100
	---help---
		The temperature (in whole °C) above which the DTS window comparator will
		assert the high‑threshold flag (TS1_ITHF).  Must be >= LOW_THRESHOLD.

config STM32H5_DTS_ITEN_ITEF
	bool "Enable DTS end‑of‑measurement interrupt (TS1_ITEF)"
	default y
	---help---
		Enable the synchronous “end of measurement” interrupt for the
		digital temperature sensor.  When set, the driver will attach
		and unmask TS1_ITEF and will call your ISR on every fresh sample.

config STM32H5_DTS_ITEN_ITLF
	bool "Enable DTS low‑threshold interrupt (TS1_ITLF)"
	default n
	---help---
		Enable the synchronous “low threshold crossed” interrupt for the
		digital temperature sensor.  When set, the driver will unmask
		TS1_ITLF so you can get notified whenever the measured value
		drops below your programmed low‑threshold.

config STM32H5_DTS_ITEN_ITHF
	bool "Enable DTS high‑threshold interrupt (TS1_ITHF)"
	default n
	---help---
		Enable the synchronous “high threshold crossed” interrupt for the
		digital temperature sensor.  When set, the driver will unmask
		TS1_ITHF so you can get notified whenever the measured value
		exceeds your programmed high‑threshold.

config STM32H5_DTS_AITEN_AITEF
	bool "Enable DTS asynchronous end‑of‑measurement interrupt (TS1_AITEF)"
	depends on STM32H5_DTS_REFCLK_LSE
	default n
	---help---
		Enable the asynchronous end‑of‑measurement interrupt.  This will
		set TS1_AITEEN in DTS_ITENR and cause an _asynchronous_ wakeup
		event when a conversion completes (in Stop/Sleep modes).

config STM32H5_DTS_AITEN_AITLF
	bool "Enable DTS asynchronous low‑threshold interrupt (TS1_AITLF)"
	depends on STM32H5_DTS_REFCLK_LSE
	default n
	---help---
		Enable the asynchronous low‑threshold comparator interrupt.  This
		will set TS1_AITLEN in DTS_ITENR and generate a wakeup event
		when the measurement drops below your low threshold.

config STM32H5_DTS_AITEN_AITHF
	bool "Enable DTS asynchronous high‑threshold interrupt (TS1_AITHF)"
	depends on STM32H5_DTS_REFCLK_LSE
	default n
	---help---
		Enable the asynchronous high‑threshold comparator interrupt.  This
		will set TS1_AITHEN in DTS_ITENR and generate a wakeup event
		when the measurement exceeds your high threshold.

endmenu # DTS Configuration

config STM32H5_FLASH_PREFETCH
	bool "Enable FLASH Pre-fetch"
	default y
	---help---
		Enable FLASH prefetch

menu "ICACHE Configuration"
	depends on STM32H5_ICACHE

config STM32H5_ICACHE_MONITOR_EN
	bool "Enable ICACHE Hit/Miss Counters"
	default n

config STM32H5_ICACHE_DIRECT
	bool "Enable 1-Way Direct Mapped Cache (N-Way = default)"
	default n

menu "ICACHE Interrupt Configuration"
	depends on STM32H5_ICACHE

config STM32H5_ICACHE_INV_INT
	bool "Enable interrupts on full invalidation completion."
	default n

config STM32H5_ICACHE_ERR_INT
	bool "Enable interrupts on occurrences of cache errors."
	default n

endmenu # ICACHE Interrupt Configuration

menu "ICACHE Region Configuration"
	depends on STM32H5_ICACHE

config STM32H5_ICACHE_REGION0
	bool "Enable Configuration of ICACHE Region 0"
	default n

config STM32H5_ICACHE_REGION1
	bool "Enable Configuration of ICACHE Region 1"
	default n

config STM32H5_ICACHE_REGION2
	bool "Enable Configuration of ICACHE Region 2"
	default n

config STM32H5_ICACHE_REGION3
	bool "Enable Configuration of ICACHE Region 3"
	default n

menu "Region 0 Configuration"
	depends on STM32H5_ICACHE_REGION0 && STM32H5_HAVE_ICACHE_REMAP

config STM32H5_ICACHE_REGION0_BADDR
	hex "ICACHE Region 0 Base Address Bits [28:21]"
	default 0
	range 0 255
	depends on STM32H5_ICACHE_REGION0
	---help---
		Set bits [28:21] of the base address for ICACHE Region 0.

config STM32H5_ICACHE_REGION0_RSIZE
	int "ICACHE Region 0 Size"
	default 1
	range 1 7
	depends on STM32H5_ICACHE_REGION0
	---help---
		Set the size of Region 0.
                1 = 2 Mbytes, 2 = 4 Mbytes, 3 = 8 Mbytes, 4 = 16 Mbytes,
                5 = 2 Mbytes, 6 = 64 Mbytes, 7 = 128 Mbytes.

config STM32H5_ICACHE_REGION0_REMAPADDR
	hex "ICACHE Region 0 Remap Address Bits [31:21]"
	default 0
	range 0 2047
	depends on STM32H5_ICACHE_REGION0
	---help---
		Set bits [31:21] of ICACHE Region 0 Remap Address..

config STM32H5_ICACHE_REGION0_MSTSEL
	int "ICACHE Region 0 Master Select (0 or 1)"
	default 0
	range 0 1
	depends on STM32H5_ICACHE_REGION0
	---help---
		Select ICACHE Region 0 Master 1 (0) or Master 2 (1).

config STM32H5_ICACHE_REGION0_HBURST
	int "ICACHE Region 0 Output Burst Type (0 = Wrap, 1 = Incr)"
	default 0
	range 0 1
	depends on STM32H5_ICACHE_REGION0
	---help---
		Select Wrap (0) or Increment (1) Output Burst Type.

endmenu # Region 0 Configuration

menu "Region 1 Configuration"
	depends on STM32H5_ICACHE_REGION1 && STM32H5_HAVE_ICACHE_REMAP

config STM32H5_ICACHE_REGION1_BADDR
	hex "ICACHE Region 1 Base Address Bits [28:21]"
	default 0
	range 0 255
	depends on STM32H5_ICACHE_REGION1
	---help---
		Set bits [28:21] of the base address for ICACHE Region 1.

config STM32H5_ICACHE_REGION1_RSIZE
	int "ICACHE Region 1 Size"
	default 1
	range 1 7
	depends on STM32H5_ICACHE_REGION1
	---help---
		Set the size of Region 1.
                1 = 2 Mbytes, 2 = 4 Mbytes, 3 = 8 Mbytes, 4 = 16 Mbytes,
                5 = 2 Mbytes, 6 = 64 Mbytes, 7 = 128 Mbytes.

config STM32H5_ICACHE_REGION1_REMAPADDR
	hex "ICACHE Region 1 Remap Address Bits [31:21]"
	default 0
	range 0 2047
	depends on STM32H5_ICACHE_REGION1
	---help---
		Set bits [31:21] of ICACHE Region 1 Remap Address..

config STM32H5_ICACHE_REGION1_MSTSEL
	int "ICACHE Region 1 Master Select (0 or 1)"
	default 0
	range 0 1
	depends on STM32H5_ICACHE_REGION1
	---help---
		Select ICACHE Region 1 Master 1 (0) or Master 2 (1).

config STM32H5_ICACHE_REGION1_HBURST
	int "ICACHE Region 1 Output Burst Type (0 = Wrap, 1 = Incr)"
	default 0
	range 0 1
	depends on STM32H5_ICACHE_REGION1
	---help---
		Select Wrap (0) or Increment (1) Output Burst Type.

endmenu # Region 1 Configuration

menu "Region 2 Configuration"
	depends on STM32H5_ICACHE_REGION2 && STM32H5_HAVE_ICACHE_REMAP

config STM32H5_ICACHE_REGION2_BADDR
	hex "ICACHE Region 2 Base Address Bits [28:21]"
	default 0
	range 0 255
	depends on STM32H5_ICACHE_REGION2
	---help---
		Set bits [28:21] of the base address for ICACHE Region 2.

config STM32H5_ICACHE_REGION2_RSIZE
	int "ICACHE Region 2 Size"
	default 1
	range 1 7
	depends on STM32H5_ICACHE_REGION2
	---help---
		Set the size of Region 2.
                1 = 2 Mbytes, 2 = 4 Mbytes, 3 = 8 Mbytes, 4 = 16 Mbytes,
                5 = 2 Mbytes, 6 = 64 Mbytes, 7 = 128 Mbytes.

config STM32H5_ICACHE_REGION2_REMAPADDR
	hex "ICACHE Region 2 Remap Address Bits [31:21]"
	default 0
	range 0 2047
	depends on STM32H5_ICACHE_REGION2
	---help---
		Set bits [31:21] of ICACHE Region 2 Remap Address..

config STM32H5_ICACHE_REGION2_MSTSEL
	int "ICACHE Region 2 Master Select (0 or 1)"
	default 0
	range 0 1
	depends on STM32H5_ICACHE_REGION2
	---help---
		Select ICACHE Region 2 Master 1 (0) or Master 2 (1).

config STM32H5_ICACHE_REGION2_HBURST
	int "ICACHE Region 2 Output Burst Type (0 = Wrap, 1 = Incr)"
	default 0
	range 0 1
	depends on STM32H5_ICACHE_REGION2
	---help---
		Select Wrap (0) or Increment (1) Output Burst Type.

endmenu # Region 2 Configuration

menu "Region 3 Configuration"
	depends on STM32H5_ICACHE_REGION3 && STM32H5_HAVE_ICACHE_REMAP

config STM32H5_ICACHE_REGION3_BADDR
	hex "ICACHE Region 3 Base Address Bits [28:21]"
	default 0
	range 0 255
	depends on STM32H5_ICACHE_REGION3
	---help---
		Set bits [28:21] of the base address for ICACHE Region 3.

config STM32H5_ICACHE_REGION3_RSIZE
	int "ICACHE Region 3 Size"
	default 1
	range 1 7
	depends on STM32H5_ICACHE_REGION3
	---help---
		Set the size of Region 3.
                1 = 2 Mbytes, 2 = 4 Mbytes, 3 = 8 Mbytes, 4 = 16 Mbytes,
                5 = 2 Mbytes, 6 = 64 Mbytes, 7 = 128 Mbytes.

config STM32H5_ICACHE_REGION3_REMAPADDR
	hex "ICACHE Region 3 Remap Address Bits [31:21]"
	default 0
	range 0 2047
	depends on STM32H5_ICACHE_REGION3
	---help---
		Set bits [31:21] of ICACHE Region 3 Remap Address..

config STM32H5_ICACHE_REGION3_MSTSEL
	int "ICACHE Region 3 Master Select (0 or 1)"
	default 0
	range 0 1
	depends on STM32H5_ICACHE_REGION3
	---help---
		Select ICACHE Region 3 Master 1 (0) or Master 2 (1).

config STM32H5_ICACHE_REGION3_HBURST
	int "ICACHE Region 3 Output Burst Type (0 = Wrap, 1 = Incr)"
	default 0
	range 0 1
	depends on STM32H5_ICACHE_REGION3
	---help---
		Select Wrap (0) or Increment (1) Output Burst Type.

endmenu # Region 3 Configuration

endmenu # ICACHE Region Configuration

endmenu # ICACHE Configuration

config STM32H5_DISABLE_IDLE_SLEEP_DURING_DEBUG
	bool "Disable IDLE Sleep (WFI) in debug mode"
	default n
	---help---
		In debug configuration, disables the WFI instruction in the IDLE loop
		to prevent the JTAG from disconnecting.  With some JTAG debuggers, such
		as the ST-LINK2 with OpenOCD, if the ARM is put to sleep via the WFI
		instruction, the debugger will disconnect, terminating the debug session.

config ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG
	bool "Custom clock configuration"
	default n
	---help---
		Enables special, board-specific STM32 clock configuration.

menu "ADC Configuration"
	depends on STM32H5_ADC

config STM32H5_ADC_MAX_SAMPLES
	int "The maximum number of channels that can be sampled"
	default 16
	---help---
		The maximum number of samples which can be handled without
		overrun depends on various factors. This is the user's
		responsibility to correctly select this value.
		Since the interface to update the sampling time is available
		for all supported devices, the user can change the default
		values in the board initialization logic and avoid ADC overrun.

config STM32H5_ADC1_RESOLUTION
	int "ADC1 resolution"
	depends on STM32H5_ADC1
	default 0
	range 0 3
	---help---
		ADC1 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit

config STM32H5_ADC1_DMA
	bool "ADC1 DMA Enable"
	depends on STM32H5_ADC1 && STM32H5_DMA
	default n
	---help---
		If DMA is selected, then the ADC may be configured to support DMA
		transfer, which is necessary if multiple channels are read or if
		very high trigger frequencies are used.

config STM32H5_ADC1_DMA_BATCH
	int "ADC1 DMA number of conversions"
	depends on STM32H5_ADC1 && STM32H5_ADC1_DMA
	default 1
	---help---
		This option allows you to select the number of regular group conversions
		that will trigger a DMA callback transerring data to the upper-half driver.
		By default, this value is 1, which means that data is transferred after
		each group conversion.

config STM32H5_ADC1_DMA_CFG
	bool "ADC1 DMA configuration"
	depends on STM32H5_ADC1 && STM32H5_ADC1_DMA
	default n
	---help---
		0 - ADC1 DMA in One Shot Mode, 1 - ADC1 DMA in Circular Mode

config STM32H5_ADC1_OVERSAMPLE
	bool "Enable ADC1 hardware oversampling support"
	depends on STM32H5_ADC1
	default n
	---help---
		Enable the on-chip ADC oversampling/accumulation block (CFGR2.OVSE).
		Only STM32G0 and STM32L0 series include this hardware block.

if STM32H5_ADC1_OVERSAMPLE

config STM32H5_ADC1_TROVS
	bool "Enable triggered oversampling (CFGR2.TROVS)"
	default n
	---help---
		If set, oversampling will only occur when a trigger event occurs.
		If not set, oversampling occurs continuously (TOVS=0).

config STM32H5_ADC1_OVSR
	int "Oversampling ratio (CFGR2.OVSR)"
	default 0
	range 0 7
	---help---
		Sets the oversampling ratio as 2^(OVSR+1). For example:
		0 -> 2×
		1 -> 4×
		2 -> 8×
		...
		7 -> 256×

config STM32H5_ADC1_OVSS
	int "Oversampling right-shift bits (CFGR2.OVSS)"
	default 0
	range 0 8
	---help---
		Sets how many bits the accumulated result is right-shifted.
		Max of 8-bits.

endif # STM32H5_ADC1_OVERSAMPLE

config STM32H5_ADC2_RESOLUTION
	int "ADC2 resolution"
	depends on STM32H5_ADC2
	default 0
	range 0 3
	---help---
		ADC1 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit

config STM32H5_ADC2_DMA
	bool "ADC2 DMA Enable"
	depends on STM32H5_ADC2 && STM32H5_DMA
	default n
	---help---
		If DMA is selected, then the ADC may be configured to support DMA
		transfer, which is necessary if multiple channels are read or if
		very high trigger frequencies are used.

config STM32H5_ADC2_DMA_BATCH
	int "ADC2 DMA number of conversions"
	depends on STM32H5_ADC2 && STM32H5_ADC2_DMA
	default 1
	---help---
		This option allows you to select the number of regular group conversions
		that will trigger a DMA callback transerring data to the upper-half driver.
		By default, this value is 1, which means that data is transferred after
		each group conversion.

config STM32H5_ADC2_DMA_CFG
	int "ADC2 DMA configuration"
	depends on STM32H5_ADC2_DMA && STM32H5_DMA
	range 0 1
	default 0
	---help---
		0 - ADC2 DMA in One Shot Mode, 1 - ADC2 DMA in Circular Mode

config STM32H5_ADC2_OVERSAMPLE
	bool "Enable ADC2 hardware oversampling support"
	depends on STM32H5_ADC2
	default n
	---help---
		Enable the on-chip ADC oversampling/accumulation block (CFGR2.OVSE).
		Only STM32G0 and STM32L0 series include this hardware block.

if STM32H5_ADC2_OVERSAMPLE

config STM32H5_ADC2_TROVS
	bool "Enable triggered oversampling (CFGR2.TROVS)"
	default n
	---help---
		If set, oversampling will only occur when a trigger event occurs.
		If not set, oversampling occurs continuously (TOVS=0).

config STM32H5_ADC2_OVSR
	int "Oversampling ratio (CFGR2.OVSR)"
	default 0
	range 0 7
	---help---
		Sets the oversampling ratio as 2^(OVSR+1). For example:
		0 -> 2×
		1 -> 4×
		2 -> 8×
		...
		7 -> 256×

config STM32H5_ADC2_OVSS
	int "Oversampling right-shift bits (CFGR2.OVSS)"
	default 0
	range 0 8
	---help---
		Sets how many bits the accumulated result is right-shifted.
		Max of 8-bits.

endif # STM32H5_ADC2_OVERSAMPLE

endmenu # ADC Configuration

menu "SPI Configuration"
	depends on STM32H5_SPI

config STM32H5_SPI_INTERRUPTS
	bool "Interrupt driver SPI"
	default n
	---help---
		Select to enable interrupt driven SPI support. Non-interrupt-driven,
		poll-waiting is recommended if the interrupt rate would be too high in
		the interrupt driven case.

config STM32H5_SPI_DMATHRESHOLD
	int "SPI DMA threshold"
	default 4
	depends on STM32H5_SPI_DMA
	---help---
		When SPI DMA is enabled, small DMA transfers will still be performed
		by polling logic.  But we need a threshold value to determine what
		is small.

config STM32H5_SPI1_DMA
	bool "SPI1 DMA"
	default n
	depends on STM32H5_SPI1 && !STM32H5_SPI_INTERRUPT
	select STM32H5_SPI_DMA
	---help---
		Use DMA to improve SPI1 transfer performance.  Cannot be used with STM32H5_SPI_INTERRUPT

config STM32H5_SPI1_DMA_BUFFER
	int "SPI1 DMA buffer size"
	default 0
	depends on STM32H5_SPI1_DMA
	---help---
		Add a properly aligned DMA buffer for RX and TX DMA for SPI1.

config STM32H5_SPI1_COMMTYPE
	int "SPI1 Operation mode"
	default 0
	range 0 3
	depends on STM32H5_SPI1
	---help---
		Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3)

config STM32H5_SPI2_DMA
	bool "SPI2 DMA"
	default n
	depends on STM32H5_SPI2 && !STM32H5_SPI_INTERRUPT
	select STM32H5_SPI_DMA
	---help---
		Use DMA to improve SPI2 transfer performance.  Cannot be used with STM32H5_SPI_INTERRUPT

config STM32H5_SPI2_DMA_BUFFER
	int "SPI2 DMA buffer size"
	default 0
	depends on STM32H5_SPI2_DMA
	---help---
		Add a properly aligned DMA buffer for RX and TX DMA for SPI2.

config STM32H5_SPI2_COMMTYPE
	int "SPI2 Operation mode"
	default 0
	range 0 3
	depends on STM32H5_SPI2
	---help---
		Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3)

config STM32H5_SPI3_DMA
	bool "SPI3 DMA"
	default n
	depends on STM32H5_SPI3 && !STM32H5_SPI_INTERRUPT
	select STM32H5_SPI_DMA
	---help---
		Use DMA to improve SPI3 transfer performance.  Cannot be used with STM32H5_SPI_INTERRUPT

config STM32H5_SPI3_DMA_BUFFER
	int "SPI3 DMA buffer size"
	default 0
	depends on STM32H5_SPI3_DMA
	---help---
		Add a properly aligned DMA buffer for RX and TX DMA for SPI3.

config STM32H5_SPI3_COMMTYPE
	int "SPI3 Operation mode"
	default 0
	range 0 3
	depends on STM32H5_SPI3
	---help---
		Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3)

config STM32H5_SPI4_DMA
	bool "SPI4 DMA"
	default n
	depends on STM32H5_SPI4 && !STM32H5_SPI_INTERRUPT
	select STM32H5_SPI_DMA
	---help---
		Use DMA to improve SPI4 transfer performance.  Cannot be used with STM32H5_SPI_INTERRUPT

config STM32H5_SPI4_DMA_BUFFER
	int "SPI4 DMA buffer size"
	default 0
	depends on STM32H5_SPI4_DMA
	---help---
		Add a properly aligned DMA buffer for RX and TX DMA for SPI4.

config STM32H5_SPI4_COMMTYPE
	int "SPI4 Operation mode"
	default 0
	range 0 3
	depends on STM32H5_SPI4
	---help---
		Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3)

config STM32H5_SPI5_DMA
	bool "SPI5 DMA"
	default n
	depends on STM32H5_SPI5 && !STM32H5_SPI_INTERRUPT
	select STM32H5_SPI_DMA
	---help---
		Use DMA to improve SPI5 transfer performance.  Cannot be used with STM32H5_SPI_INTERRUPT

config STM32H5_SPI5_DMA_BUFFER
	int "SPI5 DMA buffer size"
	default 0
	depends on STM32H5_SPI5_DMA
	---help---
		Add a properly aligned DMA buffer for RX and TX DMA for SPI5.

config STM32H5_SPI5_COMMTYPE
	int "SPI5 Operation mode"
	default 0
	range 0 3
	depends on STM32H5_SPI5
	---help---
		Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3)

config STM32H5_SPI6_DMA
	bool "SPI6 DMA"
	default n
	depends on STM32H5_SPI6 && !STM32H5_SPI_INTERRUPT
	select STM32H5_SPI_DMA
	---help---
		Use DMA to improve SPI6 transfer performance.  Cannot be used with STM32H5_SPI_INTERRUPT

config STM32H5_SPI6_DMA_BUFFER
	int "SPI6 DMA buffer size"
	default 0
	depends on STM32H5_SPI6_DMA
	---help---
		Add a properly aligned DMA buffer for RX and TX DMA for SPI6.

config STM32H5_SPI6_COMMTYPE
	int "SPI6 Operation mode"
	default 0
	range 0 3
	depends on STM32H5_SPI6
	---help---
		Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3)

endmenu # "SPI Configuration"

menu "Timer Configuration"

if SCHED_TICKLESS

config STM32H5_TICKLESS_TIMER
	int "Tickless hardware timer"
	default 2
	range 1 17
	---help---
		If the Tickless OS feature is enabled, then one clock must be
		assigned to provided the timer needed by the OS.

config STM32H5_TICKLESS_CHANNEL
	int "Tickless timer channel"
	default 1
	range 1 4
	---help---
		If the Tickless OS feature is enabled, the one clock must be
		assigned to provided the free-running timer needed by the OS
		and one channel on that clock is needed to handle intervals.

endif # SCHED_TICKLESS

config STM32H5_ONESHOT
	bool "TIM one-shot wrapper"
	default n
	---help---
		Enable a wrapper around the low level timer/counter functions to
		support one-shot timer.

config STM32H5_ONESHOT_MAXTIMERS
	int "Maximum number of oneshot timers"
	default 1
	range 1 8
	depends on STM32H5_ONESHOT
	---help---
		Determines the maximum number of oneshot timers that can be
		supported.  This setting pre-allocates some minimal support for each
		of the timers and places an upper limit on the number of oneshot
		timers that you can use.

config STM32H5_PWM_LL_OPS
	bool "PWM low-level operations"
	default n
	---help---
		Enable low-level PWM ops.

config STM32H5_TIM1_PWM
	bool "TIM1 PWM"
	default n
	depends on STM32H5_TIM1
	select STM32H5_PWM
	---help---
		Reserve timer 1 for use by PWM

		Timer devices may be used for different purposes.  One special purpose is
		to generate modulated outputs for such things as motor control.  If STM32H5_TIM1
		is defined then THIS following may also be defined to indicate that
		the timer is intended to be used for pulsed output modulation.

if STM32H5_TIM1_PWM

config STM32H5_TIM1_MODE
	int "TIM1 Mode"
	default 0
	range 0 4
	---help---
		Specifies the timer mode.

config STM32H5_TIM1_LOCK
	int "TIM1 Lock Level Configuration"
	default 0
	range 0 3
	---help---
		Timer 1 lock level configuration

config STM32H5_TIM1_TDTS
	int "TIM1 t_DTS Division"
	default 0
	range 0 2
	---help---
		Timer 1 dead-time and sampling clock (t_DTS) division

config STM32H5_TIM1_DEADTIME
	int "TIM1 Initial Dead-time"
	default 0
	range 0 255
	---help---
		Timer 1 initial dead-time

if STM32H5_PWM_MULTICHAN

config STM32H5_TIM1_CHANNEL1
	bool "TIM1 Channel 1"
	default n
	---help---
		Enables channel 1.

if STM32H5_TIM1_CHANNEL1

config STM32H5_TIM1_CH1MODE
	int "TIM1 Channel 1 Mode"
	default 6
	range 0 11
	---help---
		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.

config STM32H5_TIM1_CH1OUT
	bool "TIM1 Channel 1 Output"
	default n
	---help---
		Enables channel 1 output.

config STM32H5_TIM1_CH1NOUT
	bool "TIM1 Channel 1 Complementary Output"
	default n
	---help---
		Enables channel 1 Complementary Output.

endif # STM32H5_TIM1_CHANNEL1

config STM32H5_TIM1_CHANNEL2
	bool "TIM1 Channel 2"
	default n
	---help---
		Enables channel 2.

if STM32H5_TIM1_CHANNEL2

config STM32H5_TIM1_CH2MODE
	int "TIM1 Channel 2 Mode"
	default 6
	range 0 11
	---help---
		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.

config STM32H5_TIM1_CH2OUT
	bool "TIM1 Channel 2 Output"
	default n
	---help---
		Enables channel 2 output.

config STM32H5_TIM1_CH2NOUT
	bool "TIM1 Channel 2 Complementary Output"
	default n
	---help---
		Enables channel 2 Complementary Output.

endif # STM32H5_TIM1_CHANNEL2

config STM32H5_TIM1_CHANNEL3
	bool "TIM1 Channel 3"
	default n
	---help---
		Enables channel 3.

if STM32H5_TIM1_CHANNEL3

config STM32H5_TIM1_CH3MODE
	int "TIM1 Channel 3 Mode"
	default 6
	range 0 11
	---help---
		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.

config STM32H5_TIM1_CH3OUT
	bool "TIM1 Channel 3 Output"
	default n
	---help---
		Enables channel 3 output.

config STM32H5_TIM1_CH3NOUT
	bool "TIM1 Channel 3 Complementary Output"
	default n
	---help---
		Enables channel 3 Complementary Output.

endif # STM32H5_TIM1_CHANNEL3

config STM32H5_TIM1_CHANNEL4
	bool "TIM1 Channel 4"
	default n
	---help---
		Enables channel 4.

if STM32H5_TIM1_CHANNEL4

config STM32H5_TIM1_CH4MODE
	int "TIM1 Channel 4 Mode"
	default 6
	range 0 11
	---help---
		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.

config STM32H5_TIM1_CH4OUT
	bool "TIM1 Channel 4 Output"
	default n
	---help---
		Enables channel 4 output.

endif # STM32H5_TIM1_CHANNEL4

config STM32H5_TIM1_CHANNEL5
	bool "TIM1 Channel 5 (internal)"
	default n
	---help---
		Enables channel 5 (not available externally)

if STM32H5_TIM1_CHANNEL5

config STM32H5_TIM1_CH5MODE
	int "TIM1 Channel 5 Mode"
	default 6
	range 0 11
	---help---
		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.

config STM32H5_TIM1_CH5OUT
	bool "TIM1 Channel 5 Output"
	default n
	---help---
		Enables channel 5 output.

endif # STM32H5_TIM1_CHANNEL5

config STM32H5_TIM1_CHANNEL6
	bool "TIM1 Channel 6 (internal)"
	default n
	---help---
		Enables channel 6 (not available externally)

if STM32H5_TIM1_CHANNEL6

config STM32H5_TIM1_CH6MODE
	int "TIM1 Channel 6 Mode"
	default 6
	range 0 11
	---help---
		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.

config STM32H5_TIM1_CH6OUT
	bool "TIM1 Channel 6 Output"
	default n
	---help---
		Enables channel 6 output.

endif # STM32H5_TIM1_CHANNEL6

endif # STM32H5_PWM_MULTICHAN

if !STM32H5_PWM_MULTICHAN

config STM32H5_TIM1_CHANNEL
	int "TIM1 PWM Output Channel"
	default 1
	range 1 4
	---help---
		If TIM1 is enabled for PWM usage, you also need specifies the timer output
		channel {1,..,4}

if STM32H5_TIM1_CHANNEL = 1

config STM32H5_TIM1_CH1OUT
	bool "TIM1 Channel 1 Output"
	default n
	---help---
		Enables channel 1 output.

config STM32H5_TIM1_CH1NOUT
	bool "TIM1 Channel 1 Complementary Output"
	default n
	---help---
		Enables channel 1 Complementary Output.

endif # STM32H5_TIM1_CHANNEL = 1

if STM32H5_TIM1_CHANNEL = 2

config STM32H5_TIM1_CH2OUT
	bool "TIM1 Channel 2 Output"
	default n
	---help---
		Enables channel 2 output.

config STM32H5_TIM1_CH2NOUT
	bool "TIM1 Channel 2 Complementary Output"
	default n
	---help---
		Enables channel 2 Complementary Output.

endif # STM32H5_TIM1_CHANNEL = 2

if STM32H5_TIM1_CHANNEL = 3

config STM32H5_TIM1_CH3OUT
	bool "TIM1 Channel 3 Output"
	default n
	---help---
		Enables channel 3 output.

config STM32H5_TIM1_CH3NOUT
	bool "TIM1 Channel 3 Complementary Output"
	default n
	---help---
		Enables channel 3 Complementary Output.

endif # STM32H5_TIM1_CHANNEL = 3

if STM32H5_TIM1_CHANNEL = 4

config STM32H5_TIM1_CH4OUT
	bool "TIM1 Channel 4 Output"
	default n
	---help---
		Enables channel 4 output.

endif # STM32H5_TIM1_CHANNEL = 4

config STM32H5_TIM1_CHMODE
	int "TIM1 Channel Mode"
	default 6
	range 0 11
	---help---
		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.

endif # !STM32H5_PWM_MULTICHAN

endif # STM32H5_TIM1_PWM

config STM32H5_TIM2_PWM
	bool "TIM2 PWM"
	default n
	depends on STM32H5_TIM2
	select STM32H5_PWM
	---help---
		Reserve timer 2 for use by PWM

		Timer devices may be used for different purposes.  One special purpose is
		to generate modulated outputs for such things as motor control.  If STM32H5_TIM2
		is defined then THIS following may also be defined to indicate that
		the timer is intended to be used for pulsed output modulation.

if STM32H5_TIM2_PWM

config STM32H5_TIM2_MODE
	int "TIM2 Mode"
	default 0
	range 0 4
	---help---
		Specifies the timer mode.

if STM32H5_PWM_MULTICHAN

config STM32H5_TIM2_CHANNEL1
	bool "TIM2 Channel 1"
	default n
	---help---
		Enables channel 1.

if STM32H5_TIM2_CHANNEL1

config STM32H5_TIM2_CH1MODE
	int "TIM2 Channel 1 Mode"
	default 6
	range 0 11
	---help---
		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.

config STM32H5_TIM2_CH1OUT
	bool "TIM2 Channel 1 Output"
	default n
	---help---
		Enables channel 1 output.

endif # STM32H5_TIM2_CHANNEL1

config STM32H5_TIM2_CHANNEL2
	bool "TIM2 Channel 2"
	default n
	---help---
		Enables channel 2.

if STM32H5_TIM2_CHANNEL2

config STM32H5_TIM2_CH2MODE
	int "TIM2 Channel 2 Mode"
	default 6
	range 0 11
	---help---
		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.

config STM32H5_TIM2_CH2OUT
	bool "TIM2 Channel 2 Output"
	default n
	---help---
		Enables channel 2 output.

endif # STM32H5_TIM2_CHANNEL2

config STM32H5_TIM2_CHANNEL3
	bool "TIM2 Channel 3"
	default n
	---help---
		Enables channel 3.

if STM32H5_TIM2_CHANNEL3

config STM32H5_TIM2_CH3MODE
	int "TIM2 Channel 3 Mode"
	default 6
	range 0 11
	---help---
		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.

config STM32H5_TIM2_CH3OUT
	bool "TIM2 Channel 3 Output"
	default n
	---help---
		Enables channel 3 output.

endif # STM32H5_TIM2_CHANNEL3

config STM32H5_TIM2_CHANNEL4
	bool "TIM2 Channel 4"
	default n
	---help---
		Enables channel 4.

if STM32H5_TIM2_CHANNEL4

config STM32H5_TIM2_CH4MODE
	int "TIM2 Channel 4 Mode"
	default 6
	range 0 11
	---help---
		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.

config STM32H5_TIM2_CH4OUT
	bool "TIM2 Channel 4 Output"
	default n
	---help---
		Enables channel 4 output.

endif # STM32H5_TIM2_CHANNEL4

endif # STM32H5_PWM_MULTICHAN

if !STM32H5_PWM_MULTICHAN

config STM32H5_TIM2_CHANNEL
	int "TIM2 PWM Output Channel"
	default 1
	range 1 4
	---help---
		If TIM2 is enabled for PWM usage, you also need specifies the timer output
		channel {1,..,4}

if STM32H5_TIM2_CHANNEL = 1

config STM32H5_TIM2_CH1OUT
	bool "TIM2 Channel 1 Output"
	default n
	---help---
		Enables channel 1 output.

endif # STM32H5_TIM2_CHANNEL = 1

if STM32H5_TIM2_CHANNEL = 2

config STM32H5_TIM2_CH2OUT
	bool "TIM2 Channel 2 Output"
	default n
	---help---
		Enables channel 2 output.

endif # STM32H5_TIM2_CHANNEL = 2

if STM32H5_TIM2_CHANNEL = 3

config STM32H5_TIM2_CH3OUT
	bool "TIM2 Channel 3 Output"
	default n
	---help---
		Enables channel 3 output.

endif # STM32H5_TIM2_CHANNEL = 3

if STM32H5_TIM2_CHANNEL = 4

config STM32H5_TIM2_CH4OUT
	bool "TIM2 Channel 4 Output"
	default n
	---help---
		Enables channel 4 output.

endif # STM32H5_TIM2_CHANNEL = 4

config STM32H5_TIM2_CHMODE
	int "TIM2 Channel Mode"
	default 6
	range 0 11
	---help---
		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.

endif # !STM32H5_PWM_MULTICHAN

endif # STM32H5_TIM2_PWM

config STM32H5_TIM3_PWM
	bool "TIM3 PWM"
	default n
	depends on STM32H5_TIM3
	select STM32H5_PWM
	---help---
		Reserve timer 3 for use by PWM

		Timer devices may be used for different purposes.  One special purpose is
		to generate modulated outputs for such things as motor control.  If STM32H5_TIM3
		is defined then THIS following may also be defined to indicate that
		the timer is intended to be used for pulsed output modulation.

if STM32H5_TIM3_PWM

config STM32H5_TIM3_MODE
	int "TIM3 Mode"
	default 0
	range 0 4
	---help---
		Specifies the timer mode.

if STM32H5_PWM_MULTICHAN

config STM32H5_TIM3_CHANNEL1
	bool "TIM3 Channel 1"
	default n
	---help---
		Enables channel 1.

if STM32H5_TIM3_CHANNEL1

config STM32H5_TIM3_CH1MODE
	int "TIM3 Channel 1 Mode"
	default 6
	range 0 11
	---help---
		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.

config STM32H5_TIM3_CH1OUT
	bool "TIM3 Channel 1 Output"
	default n
	---help---
		Enables channel 1 output.

endif # STM32H5_TIM3_CHANNEL1

config STM32H5_TIM3_CHANNEL2
	bool "TIM3 Channel 2"
	default n
	---help---
		Enables channel 2.

if STM32H5_TIM3_CHANNEL2

config STM32H5_TIM3_CH2MODE
	int "TIM3 Channel 2 Mode"
	default 6
	range 0 11
	---help---
		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.

config STM32H5_TIM3_CH2OUT
	bool "TIM3 Channel 2 Output"
	default n
	---help---
		Enables channel 2 output.

endif # STM32H5_TIM3_CHANNEL2

config STM32H5_TIM3_CHANNEL3
	bool "TIM3 Channel 3"
	default n
	---help---
		Enables channel 3.

if STM32H5_TIM3_CHANNEL3

config STM32H5_TIM3_CH3MODE
	int "TIM3 Channel 3 Mode"
	default 6
	range 0 11
	---help---
		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.

config STM32H5_TIM3_CH3OUT
	bool "TIM3 Channel 3 Output"
	default n
	---help---
		Enables channel 3 output.

endif # STM32H5_TIM3_CHANNEL3

config STM32H5_TIM3_CHANNEL4
	bool "TIM3 Channel 4"
	default n
	---help---
		Enables channel 4.

if STM32H5_TIM3_CHANNEL4

config STM32H5_TIM3_CH4MODE
	int "TIM3 Channel 4 Mode"
	default 6
	range 0 11
	---help---
		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.

config STM32H5_TIM3_CH4OUT
	bool "TIM3 Channel 4 Output"
	default n
	---help---
		Enables channel 4 output.

endif # STM32H5_TIM3_CHANNEL4

endif # STM32H5_PWM_MULTICHAN

if !STM32H5_PWM_MULTICHAN

config STM32H5_TIM3_CHANNEL
	int "TIM3 PWM Output Channel"
	default 1
	range 1 4
	---help---
		If TIM3 is enabled for PWM usage, you also need specifies the timer output
		channel {1,..,4}

if STM32H5_TIM3_CHANNEL = 1

config STM32H5_TIM3_CH1OUT
	bool "TIM3 Channel 1 Output"
	default n
	---help---
		Enables channel 1 output.

endif # STM32H5_TIM3_CHANNEL = 1

if STM32H5_TIM3_CHANNEL = 2

config STM32H5_TIM3_CH2OUT
	bool "TIM3 Channel 2 Output"
	default n
	---help---
		Enables channel 2 output.

endif # STM32H5_TIM3_CHANNEL = 2

if STM32H5_TIM3_CHANNEL = 3

config STM32H5_TIM3_CH3OUT
	bool "TIM3 Channel 3 Output"
	default n
	---help---
		Enables channel 3 output.

endif # STM32H5_TIM3_CHANNEL = 3

if STM32H5_TIM3_CHANNEL = 4

config STM32H5_TIM3_CH4OUT
	bool "TIM3 Channel 4 Output"
	default n
	---help---
		Enables channel 4 output.

endif # STM32H5_TIM3_CHANNEL = 4

config STM32H5_TIM3_CHMODE
	int "TIM3 Channel Mode"
	default 6
	range 0 11
	---help---
		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.

endif # !STM32H5_PWM_MULTICHAN

endif # STM32H5_TIM3_PWM

config STM32H5_TIM4_PWM
	bool "TIM4 PWM"
	default n
	depends on STM32H5_TIM4
	select STM32H5_PWM
	---help---
		Reserve timer 4 for use by PWM

		Timer devices may be used for different purposes.  One special purpose is
		to generate modulated outputs for such things as motor control.  If STM32H5_TIM4
		is defined then THIS following may also be defined to indicate that
		the timer is intended to be used for pulsed output modulation.

if STM32H5_TIM4_PWM

config STM32H5_TIM4_MODE
	int "TIM4 Mode"
	default 0
	range 0 4
	---help---
		Specifies the timer mode.

if STM32H5_PWM_MULTICHAN

config STM32H5_TIM4_CHANNEL1
	bool "TIM4 Channel 1"
	default n
	---help---
		Enables channel 1.

if STM32H5_TIM4_CHANNEL1

config STM32H5_TIM4_CH1MODE
	int "TIM4 Channel 1 Mode"
	default 6
	range 0 11
	---help---
		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.

config STM32H5_TIM4_CH1OUT
	bool "TIM4 Channel 1 Output"
	default n
	---help---
		Enables channel 1 output.

endif # STM32H5_TIM4_CHANNEL1

config STM32H5_TIM4_CHANNEL2
	bool "TIM4 Channel 2"
	default n
	---help---
		Enables channel 2.

if STM32H5_TIM4_CHANNEL2

config STM32H5_TIM4_CH2MODE
	int "TIM4 Channel 2 Mode"
	default 6
	range 0 11
	---help---
		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.

config STM32H5_TIM4_CH2OUT
	bool "TIM4 Channel 2 Output"
	default n
	---help---
		Enables channel 2 output.

endif # STM32H5_TIM4_CHANNEL2

config STM32H5_TIM4_CHANNEL3
	bool "TIM4 Channel 3"
	default n
	---help---
		Enables channel 3.

if STM32H5_TIM4_CHANNEL3

config STM32H5_TIM4_CH3MODE
	int "TIM4 Channel 3 Mode"
	default 6
	range 0 11
	---help---
		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.

config STM32H5_TIM4_CH3OUT
	bool "TIM4 Channel 3 Output"
	default n
	---help---
		Enables channel 3 output.

endif # STM32H5_TIM4_CHANNEL3

config STM32H5_TIM4_CHANNEL4
	bool "TIM4 Channel 4"
	default n
	---help---
		Enables channel 4.

if STM32H5_TIM4_CHANNEL4

config STM32H5_TIM4_CH4MODE
	int "TIM4 Channel 4 Mode"
	default 6
	range 0 11
	---help---
		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.

config STM32H5_TIM4_CH4OUT
	bool "TIM4 Channel 4 Output"
	default n
	---help---
		Enables channel 4 output.

endif # STM32H5_TIM4_CHANNEL4

endif # STM32H5_PWM_MULTICHAN

if !STM32H5_PWM_MULTICHAN

config STM32H5_TIM4_CHANNEL
	int "TIM4 PWM Output Channel"
	default 1
	range 1 4
	---help---
		If TIM4 is enabled for PWM usage, you also need specifies the timer output
		channel {1,..,4}

if STM32H5_TIM4_CHANNEL = 1

config STM32H5_TIM4_CH1OUT
	bool "TIM4 Channel 1 Output"
	default n
	---help---
		Enables channel 1 output.

endif # STM32H5_TIM4_CHANNEL = 1

if STM32H5_TIM4_CHANNEL = 2

config STM32H5_TIM4_CH2OUT
	bool "TIM4 Channel 2 Output"
	default n
	---help---
		Enables channel 2 output.

endif # STM32H5_TIM4_CHANNEL = 2

if STM32H5_TIM4_CHANNEL = 3

config STM32H5_TIM4_CH3OUT
	bool "TIM4 Channel 3 Output"
	default n
	---help---
		Enables channel 3 output.

endif # STM32H5_TIM4_CHANNEL = 3

if STM32H5_TIM4_CHANNEL = 4

config STM32H5_TIM4_CH4OUT
	bool "TIM4 Channel 4 Output"
	default n
	---help---
		Enables channel 4 output.

endif # STM32H5_TIM4_CHANNEL = 4

config STM32H5_TIM4_CHMODE
	int "TIM4 Channel Mode"
	default 6
	range 0 11
	---help---
		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.

endif # !STM32H5_PWM_MULTICHAN

endif # STM32H5_TIM4_PWM

config STM32H5_TIM5_PWM
	bool "TIM5 PWM"
	default n
	depends on STM32H5_TIM5
	select STM32H5_PWM
	---help---
		Reserve timer 5 for use by PWM

		Timer devices may be used for different purposes.  One special purpose is
		to generate modulated outputs for such things as motor control.  If STM32H5_TIM5
		is defined then THIS following may also be defined to indicate that
		the timer is intended to be used for pulsed output modulation.

if STM32H5_TIM5_PWM

config STM32H5_TIM5_MODE
	int "TIM5 Mode"
	default 0
	range 0 4
	---help---
		Specifies the timer mode.

if STM32H5_PWM_MULTICHAN

config STM32H5_TIM5_CHANNEL1
	bool "TIM5 Channel 1"
	default n
	---help---
		Enables channel 1.

if STM32H5_TIM5_CHANNEL1

config STM32H5_TIM5_CH1MODE
	int "TIM5 Channel 1 Mode"
	default 6
	range 0 11
	---help---
		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.

config STM32H5_TIM5_CH1OUT
	bool "TIM5 Channel 1 Output"
	default n
	---help---
		Enables channel 1 output.

endif # STM32H5_TIM5_CHANNEL1

config STM32H5_TIM5_CHANNEL2
	bool "TIM5 Channel 2"
	default n
	---help---
		Enables channel 2.

if STM32H5_TIM5_CHANNEL2

config STM32H5_TIM5_CH2MODE
	int "TIM5 Channel 2 Mode"
	default 6
	range 0 11
	---help---
		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.

config STM32H5_TIM5_CH2OUT
	bool "TIM5 Channel 2 Output"
	default n
	---help---
		Enables channel 2 output.

endif # STM32H5_TIM5_CHANNEL2

config STM32H5_TIM5_CHANNEL3
	bool "TIM5 Channel 3"
	default n
	---help---
		Enables channel 3.

if STM32H5_TIM5_CHANNEL3

config STM32H5_TIM5_CH3MODE
	int "TIM5 Channel 3 Mode"
	default 6
	range 0 11
	---help---
		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.

config STM32H5_TIM5_CH3OUT
	bool "TIM5 Channel 3 Output"
	default n
	---help---
		Enables channel 3 output.

endif # STM32H5_TIM5_CHANNEL3

config STM32H5_TIM5_CHANNEL4
	bool "TIM5 Channel 4"
	default n
	---help---
		Enables channel 4.

if STM32H5_TIM5_CHANNEL4

config STM32H5_TIM5_CH4MODE
	int "TIM5 Channel 4 Mode"
	default 6
	range 0 11
	---help---
		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.

config STM32H5_TIM5_CH4OUT
	bool "TIM5 Channel 4 Output"
	default n
	---help---
		Enables channel 4 output.

endif # STM32H5_TIM5_CHANNEL4

endif # STM32H5_PWM_MULTICHAN

if !STM32H5_PWM_MULTICHAN

config STM32H5_TIM5_CHANNEL
	int "TIM5 PWM Output Channel"
	default 1
	range 1 4
	---help---
		If TIM5 is enabled for PWM usage, you also need specifies the timer output
		channel {1,..,4}

if STM32H5_TIM5_CHANNEL = 1

config STM32H5_TIM5_CH1OUT
	bool "TIM5 Channel 1 Output"
	default n
	---help---
		Enables channel 1 output.

endif # STM32H5_TIM5_CHANNEL = 1

if STM32H5_TIM5_CHANNEL = 2

config STM32H5_TIM5_CH2OUT
	bool "TIM5 Channel 2 Output"
	default n
	---help---
		Enables channel 2 output.

endif # STM32H5_TIM5_CHANNEL = 2

if STM32H5_TIM5_CHANNEL = 3

config STM32H5_TIM5_CH3OUT
	bool "TIM5 Channel 3 Output"
	default n
	---help---
		Enables channel 3 output.

endif # STM32H5_TIM5_CHANNEL = 3

if STM32H5_TIM5_CHANNEL = 4

config STM32H5_TIM5_CH4OUT
	bool "TIM5 Channel 4 Output"
	default n
	---help---
		Enables channel 4 output.

endif # STM32H5_TIM5_CHANNEL = 4

config STM32H5_TIM5_CHMODE
	int "TIM5 Channel Mode"
	default 6
	range 0 11
	---help---
		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.

endif # !STM32H5_PWM_MULTICHAN

endif # STM32H5_TIM5_PWM

config STM32H5_TIM8_PWM
	bool "TIM8 PWM"
	default n
	depends on STM32H5_TIM8
	select STM32H5_PWM
	---help---
		Reserve timer 8 for use by PWM

		Timer devices may be used for different purposes.  One special purpose is
		to generate modulated outputs for such things as motor control.  If STM32H5_TIM8
		is defined then THIS following may also be defined to indicate that
		the timer is intended to be used for pulsed output modulation.

if STM32H5_TIM8_PWM

config STM32H5_TIM8_MODE
	int "TIM8 Mode"
	default 0
	range 0 4
	---help---
		Specifies the timer mode.

config STM32H5_TIM8_LOCK
	int "TIM8 Lock Level Configuration"
	default 0
	range 0 3
	---help---
		Timer 8 lock level configuration

config STM32H5_TIM8_DEADTIME
	int "TIM8 Initial Dead-time"
	default 0
	range 0 255
	---help---
		Timer 8 initial dead-time

config STM32H5_TIM8_TDTS
	int "TIM8 t_DTS Division"
	default 0
	range 0 2
	---help---
		Timer 8 dead-time and sampling clock (t_DTS) division

if STM32H5_PWM_MULTICHAN

config STM32H5_TIM8_CHANNEL1
	bool "TIM8 Channel 1"
	default n
	---help---
		Enables channel 1.

if STM32H5_TIM8_CHANNEL1

config STM32H5_TIM8_CH1MODE
	int "TIM8 Channel 1 Mode"
	default 6
	range 0 11
	---help---
		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.

config STM32H5_TIM8_CH1OUT
	bool "TIM8 Channel 1 Output"
	default n
	---help---
		Enables channel 1 output.

config STM32H5_TIM8_CH1NOUT
	bool "TIM8 Channel 1 Complementary Output"
	default n
	---help---
		Enables channel 1 Complementary Output.

endif # STM32H5_TIM8_CHANNEL1

config STM32H5_TIM8_CHANNEL2
	bool "TIM8 Channel 2"
	default n
	---help---
		Enables channel 2.

if STM32H5_TIM8_CHANNEL2

config STM32H5_TIM8_CH2MODE
	int "TIM8 Channel 2 Mode"
	default 6
	range 0 11
	---help---
		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.

config STM32H5_TIM8_CH2OUT
	bool "TIM8 Channel 2 Output"
	default n
	---help---
		Enables channel 2 output.

config STM32H5_TIM8_CH2NOUT
	bool "TIM8 Channel 2 Complementary Output"
	default n
	---help---
		Enables channel 2 Complementary Output.

endif # STM32H5_TIM8_CHANNEL2

config STM32H5_TIM8_CHANNEL3
	bool "TIM8 Channel 3"
	default n
	---help---
		Enables channel 3.

if STM32H5_TIM8_CHANNEL3

config STM32H5_TIM8_CH3MODE
	int "TIM8 Channel 3 Mode"
	default 6
	range 0 11
	---help---
		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.

config STM32H5_TIM8_CH3OUT
	bool "TIM8 Channel 3 Output"
	default n
	---help---
		Enables channel 3 output.

config STM32H5_TIM8_CH3NOUT
	bool "TIM8 Channel 3 Complementary Output"
	default n
	---help---
		Enables channel 3 Complementary Output.

endif # STM32H5_TIM8_CHANNEL3

config STM32H5_TIM8_CHANNEL4
	bool "TIM8 Channel 4"
	default n
	---help---
		Enables channel 4.

if STM32H5_TIM8_CHANNEL4

config STM32H5_TIM8_CH4MODE
	int "TIM8 Channel 4 Mode"
	default 6
	range 0 11
	---help---
		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.

config STM32H5_TIM8_CH4OUT
	bool "TIM8 Channel 4 Output"
	default n
	---help---
		Enables channel 4 output.

endif # STM32H5_TIM8_CHANNEL4

config STM32H5_TIM8_CHANNEL5
	bool "TIM8 Channel 5 (internal)"
	default n
	---help---
		Enables channel 5 (not available externally)

if STM32H5_TIM8_CHANNEL5

config STM32H5_TIM8_CH5MODE
	int "TIM8 Channel 5 Mode"
	default 6
	range 0 11
	---help---
		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.

config STM32H5_TIM8_CH5OUT
	bool "TIM8 Channel 5 Output"
	default n
	---help---
		Enables channel 5 output.

endif # STM32H5_TIM8_CHANNEL5

config STM32H5_TIM8_CHANNEL6
	bool "TIM8 Channel 6 (internal)"
	default n
	---help---
		Enables channel 6 (not available externally)

if STM32H5_TIM8_CHANNEL6

config STM32H5_TIM8_CH6MODE
	int "TIM8 Channel 6 Mode"
	default 6
	range 0 11
	---help---
		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.

config STM32H5_TIM8_CH6OUT
	bool "TIM8 Channel 6 Output"
	default n
	---help---
		Enables channel 6 output.

endif # STM32H5_TIM8_CHANNEL6

endif # STM32H5_PWM_MULTICHAN

if !STM32H5_PWM_MULTICHAN

config STM32H5_TIM8_CHANNEL
	int "TIM8 PWM Output Channel"
	default 1
	range 1 4
	---help---
		If TIM8 is enabled for PWM usage, you also need specifies the timer output
		channel {1,..,4}

if STM32H5_TIM8_CHANNEL = 1

config STM32H5_TIM8_CH1OUT
	bool "TIM8 Channel 1 Output"
	default n
	---help---
		Enables channel 1 output.

config STM32H5_TIM8_CH1NOUT
	bool "TIM8 Channel 1 Complementary Output"
	default n
	---help---
		Enables channel 1 Complementary Output.

endif # STM32H5_TIM8_CHANNEL = 1

if STM32H5_TIM8_CHANNEL = 2

config STM32H5_TIM8_CH2OUT
	bool "TIM8 Channel 2 Output"
	default n
	---help---
		Enables channel 2 output.

config STM32H5_TIM8_CH2NOUT
	bool "TIM8 Channel 2 Complementary Output"
	default n
	---help---
		Enables channel 2 Complementary Output.

endif # STM32H5_TIM8_CHANNEL = 2

if STM32H5_TIM8_CHANNEL = 3

config STM32H5_TIM8_CH3OUT
	bool "TIM8 Channel 3 Output"
	default n
	---help---
		Enables channel 3 output.

config STM32H5_TIM8_CH3NOUT
	bool "TIM8 Channel 3 Complementary Output"
	default n
	---help---
		Enables channel 3 Complementary Output.

endif # STM32H5_TIM8_CHANNEL = 3

if STM32H5_TIM8_CHANNEL = 4

config STM32H5_TIM8_CH4OUT
	bool "TIM8 Channel 4 Output"
	default n
	---help---
		Enables channel 4 output.

endif # STM32H5_TIM8_CHANNEL = 4

config STM32H5_TIM8_CHMODE
	int "TIM8 Channel Mode"
	default 6
	range 0 11
	---help---
		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.

endif # !STM32H5_PWM_MULTICHAN

endif # STM32H5_TIM8_PWM

config STM32H5_TIM12_PWM
	bool "TIM12 PWM"
	default n
	depends on STM32H5_TIM12
	select STM32H5_PWM
	---help---
		Reserve timer 12 for use by PWM

		Timer devices may be used for different purposes.  One special purpose is
		to generate modulated outputs for such things as motor control.  If STM32H5_TIM12
		is defined then THIS following may also be defined to indicate that
		the timer is intended to be used for pulsed output modulation.

if STM32H5_TIM12_PWM

if STM32H5_PWM_MULTICHAN

config STM32H5_TIM12_CHANNEL1
	bool "TIM12 Channel 1"
	default n
	---help---
		Enables channel 1.

if STM32H5_TIM12_CHANNEL1

config STM32H5_TIM12_CH1MODE
	int "TIM12 Channel 1 Mode"
	default 6
	range 0 11
	---help---
		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.

config STM32H5_TIM12_CH1OUT
	bool "TIM12 Channel 1 Output"
	default n
	---help---
		Enables channel 1 output.

endif # STM32H5_TIM12_CHANNEL1

config STM32H5_TIM12_CHANNEL2
	bool "TIM12 Channel 2"
	default n
	---help---
		Enables channel 2.

if STM32H5_TIM12_CHANNEL2

config STM32H5_TIM12_CH2MODE
	int "TIM12 Channel 2 Mode"
	default 6
	range 0 11
	---help---
		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.

config STM32H5_TIM12_CH2OUT
	bool "TIM12 Channel 2 Output"
	default n
	---help---
		Enables channel 2 output.

endif # STM32H5_TIM12_CHANNEL2

endif # STM32H5_PWM_MULTICHAN

if !STM32H5_PWM_MULTICHAN

config STM32H5_TIM12_CHANNEL
	int "TIM12 PWM Output Channel"
	default 1
	range 1 2
	---help---
		If TIM12 is enabled for PWM usage, you also need specifies the timer output
		channel {1,2}

if STM32H5_TIM12_CHANNEL = 1

config STM32H5_TIM12_CH1OUT
	bool "TIM12 Channel 1 Output"
	default n
	---help---
		Enables channel 1 output.

endif # STM32H5_TIM12_CHANNEL = 1

if STM32H5_TIM12_CHANNEL = 2

config STM32H5_TIM12_CH2OUT
	bool "TIM12 Channel 2 Output"
	default n
	---help---
		Enables channel 2 output.

endif # STM32H5_TIM12_CHANNEL = 2

config STM32H5_TIM12_CHMODE
	int "TIM12 Channel Mode"
	default 6
	range 0 11
	---help---
		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.

endif # !STM32H5_PWM_MULTICHAN

endif # STM32H5_TIM12_PWM

config STM32H5_TIM13_PWM
	bool "TIM13 PWM"
	default n
	depends on STM32H5_TIM13
	select STM32H5_PWM
	---help---
		Reserve timer 13 for use by PWM

		Timer devices may be used for different purposes.  One special purpose is
		to generate modulated outputs for such things as motor control.  If STM32H5_TIM13
		is defined then THIS following may also be defined to indicate that
		the timer is intended to be used for pulsed output modulation.

if STM32H5_TIM13_PWM

if STM32H5_PWM_MULTICHAN

config STM32H5_TIM13_CHANNEL1
	bool "TIM13 Channel 1"
	default n
	---help---
		Enables channel 1.

if STM32H5_TIM13_CHANNEL1

config STM32H5_TIM13_CH1MODE
	int "TIM13 Channel 1 Mode"
	default 6
	range 0 11
	---help---
		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.

config STM32H5_TIM13_CH1OUT
	bool "TIM13 Channel 1 Output"
	default n
	---help---
		Enables channel 1 output.

endif # STM32H5_TIM13_CHANNEL1

endif # STM32H5_PWM_MULTICHAN

if !STM32H5_PWM_MULTICHAN

config STM32H5_TIM13_CHANNEL
	int "TIM13 PWM Output Channel"
	default 1
	range 1 1
	---help---
		If TIM13 is enabled for PWM usage, you also need specifies the timer output
		channel {1}

if STM32H5_TIM13_CHANNEL = 1

config STM32H5_TIM13_CH1OUT
	bool "TIM13 Channel 1 Output"
	default n
	---help---
		Enables channel 1 output.

endif # STM32H5_TIM13_CHANNEL = 1

config STM32H5_TIM13_CHMODE
	int "TIM13 Channel Mode"
	default 6
	range 0 11
	---help---
		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.

endif # !STM32H5_PWM_MULTICHAN

endif # STM32H5_TIM13_PWM

config STM32H5_TIM14_PWM
	bool "TIM14 PWM"
	default n
	depends on STM32H5_TIM14
	select STM32H5_PWM
	---help---
		Reserve timer 14 for use by PWM

		Timer devices may be used for different purposes.  One special purpose is
		to generate modulated outputs for such things as motor control.  If STM32H5_TIM14
		is defined then THIS following may also be defined to indicate that
		the timer is intended to be used for pulsed output modulation.

if STM32H5_TIM14_PWM

if STM32H5_PWM_MULTICHAN

config STM32H5_TIM14_CHANNEL1
	bool "TIM14 Channel 1"
	default n
	---help---
		Enables channel 1.

if STM32H5_TIM14_CHANNEL1

config STM32H5_TIM14_CH1MODE
	int "TIM14 Channel 1 Mode"
	default 6
	range 0 11
	---help---
		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.

config STM32H5_TIM14_CH1OUT
	bool "TIM14 Channel 1 Output"
	default n
	---help---
		Enables channel 1 output.

endif # STM32H5_TIM14_CHANNEL1

endif # STM32H5_PWM_MULTICHAN

if !STM32H5_PWM_MULTICHAN

config STM32H5_TIM14_CHANNEL
	int "TIM14 PWM Output Channel"
	default 1
	range 1 1
	---help---
		If TIM14 is enabled for PWM usage, you also need specifies the timer output
		channel {1}

if STM32H5_TIM14_CHANNEL = 1

config STM32H5_TIM14_CH1OUT
	bool "TIM14 Channel 1 Output"
	default n
	---help---
		Enables channel 1 output.

endif # STM32H5_TIM14_CHANNEL = 1

config STM32H5_TIM14_CHMODE
	int "TIM14 Channel Mode"
	default 6
	range 0 11
	---help---
		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.

endif # !STM32H5_PWM_MULTICHAN

endif # STM32H5_TIM14_PWM

config STM32H5_TIM15_PWM
	bool "TIM15 PWM"
	default n
	depends on STM32H5_TIM15
	select STM32H5_PWM
	---help---
		Reserve timer 15 for use by PWM

		Timer devices may be used for different purposes.  One special purpose is
		to generate modulated outputs for such things as motor control.  If STM32H5_TIM15
		is defined then THIS following may also be defined to indicate that
		the timer is intended to be used for pulsed output modulation.

if STM32H5_TIM15_PWM

config STM32H5_TIM15_LOCK
	int "TIM15 Lock Level Configuration"
	default 0
	range 0 3
	---help---
		Timer 15 lock level configuration

config STM32H5_TIM15_TDTS
	int "TIM15 t_DTS Division"
	default 0
	range 0 2
	---help---
		Timer 15 dead-time and sampling clock (t_DTS) division

config STM32H5_TIM15_DEADTIME
	int "TIM15 Initial Dead-time"
	default 0
	range 0 255
	---help---
		Timer 15 initial dead-time

if STM32H5_PWM_MULTICHAN

config STM32H5_TIM15_CHANNEL1
	bool "TIM15 Channel 1"
	default n
	---help---
		Enables channel 1.

if STM32H5_TIM15_CHANNEL1

config STM32H5_TIM15_CH1MODE
	int "TIM15 Channel 1 Mode"
	default 6
	range 0 9
	---help---
		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.

config STM32H5_TIM15_CH1OUT
	bool "TIM15 Channel 1 Output"
	default n
	---help---
		Enables channel 1 output.

config STM32H5_TIM15_CH1NOUT
	bool "TIM15 Channel 1 Complementary Output"
	default n
	---help---
		Enables channel 1 Complementary Output.

endif # STM32H5_TIM15_CHANNEL1

config STM32H5_TIM15_CHANNEL2
	bool "TIM15 Channel 2"
	default n
	---help---
		Enables channel 2.

if STM32H5_TIM15_CHANNEL2

config STM32H5_TIM15_CH2MODE
	int "TIM15 Channel 2 Mode"
	default 6
	range 0 9
	---help---
		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.

config STM32H5_TIM15_CH2OUT
	bool "TIM15 Channel 2 Output"
	default n
	---help---
		Enables channel 2 output.

endif # STM32H5_TIM15_CHANNEL2

endif # STM32H5_PWM_MULTICHAN

if !STM32H5_PWM_MULTICHAN

config STM32H5_TIM15_CHANNEL
	int "TIM15 PWM Output Channel"
	default 1
	range 1 2
	---help---
		If TIM15 is enabled for PWM usage, you also need specifies the timer output
		channel {1,2}

if STM32H5_TIM15_CHANNEL = 1

config STM32H5_TIM15_CH1OUT
	bool "TIM15 Channel 1 Output"
	default n
	---help---
		Enables channel 1 output.

config STM32H5_TIM15_CH1NOUT
	bool "TIM15 Channel 1 Complementary Output"
	default n
	---help---
		Enables channel 1 Complementary Output.

endif # STM32H5_TIM15_CHANNEL = 1

if STM32H5_TIM15_CHANNEL = 2

config STM32H5_TIM15_CH2OUT
	bool "TIM15 Channel 2 Output"
	default n
	---help---
		Enables channel 2 output.

config STM32H5_TIM15_CH2NOUT
	bool "TIM15 Channel 2 Complementary Output"
	default n
	---help---
		Enables channel 2 Complementary Output.

endif # STM32H5_TIM15_CHANNEL = 2

config STM32H5_TIM15_CHMODE
	int "TIM15 Channel Mode"
	default 6
	range 0 9
	---help---
		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.

endif # !STM32H5_PWM_MULTICHAN

endif # STM32H5_TIM15_PWM

config STM32H5_TIM16_PWM
	bool "TIM16 PWM"
	default n
	depends on STM32H5_TIM16
	select STM32H5_PWM
	---help---
		Reserve timer 16 for use by PWM

		Timer devices may be used for different purposes.  One special purpose is
		to generate modulated outputs for such things as motor control.  If STM32H5_TIM16
		is defined then THIS following may also be defined to indicate that
		the timer is intended to be used for pulsed output modulation.

if STM32H5_TIM16_PWM

config STM32H5_TIM16_LOCK
	int "TIM16 Lock Level Configuration"
	default 0
	range 0 3
	---help---
		Timer 16 lock level configuration

config STM32H5_TIM16_TDTS
	int "TIM16 t_DTS division"
	default 0
	range 0 2
	---help---
		Timer 16 dead-time and sampling clock (t_DTS) division

config STM32H5_TIM16_DEADTIME
	int "TIM16 Initial Dead-time"
	default 0
	range 0 255
	---help---
		Timer 16 initial dead-time

if STM32H5_PWM_MULTICHAN

config STM32H5_TIM16_CHANNEL1
	bool "TIM16 Channel 1"
	default n
	---help---
		Enables channel 1.

if STM32H5_TIM16_CHANNEL1

config STM32H5_TIM16_CH1MODE
	int "TIM16 Channel 1 Mode"
	default 6
	range 0 7
	---help---
		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.

config STM32H5_TIM16_CH1OUT
	bool "TIM16 Channel 1 Output"
	default n
	---help---
		Enables channel 1 output.

endif # STM32H5_TIM16_CHANNEL1

endif # STM32H5_PWM_MULTICHAN

if !STM32H5_PWM_MULTICHAN

config STM32H5_TIM16_CHANNEL
	int "TIM16 PWM Output Channel"
	default 1
	range 1 1
	---help---
		If TIM16 is enabled for PWM usage, you also need specifies the timer output
		channel {1}

if STM32H5_TIM16_CHANNEL = 1

config STM32H5_TIM16_CH1OUT
	bool "TIM16 Channel 1 Output"
	default n
	---help---
		Enables channel 1 output.

endif # STM32H5_TIM16_CHANNEL = 1

config STM32H5_TIM16_CHMODE
	int "TIM16 Channel Mode"
	default 6
	range 0 7
	---help---
		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.

endif # !STM32H5_PWM_MULTICHAN

endif # STM32H5_TIM16_PWM

config STM32H5_TIM17_PWM
	bool "TIM17 PWM"
	default n
	depends on STM32H5_TIM17
	select STM32H5_PWM
	---help---
		Reserve timer 17 for use by PWM

		Timer devices may be used for different purposes.  One special purpose is
		to generate modulated outputs for such things as motor control.  If STM32H5_TIM17
		is defined then THIS following may also be defined to indicate that
		the timer is intended to be used for pulsed output modulation.

if STM32H5_TIM17_PWM

config STM32H5_TIM17_LOCK
	int "TIM17 Lock Level Configuration"
	default 0
	range 0 3
	---help---
		Timer 17 lock level configuration

config STM32H5_TIM17_TDTS
	int "TIM17 t_DTS Division"
	default 0
	range 0 2
	---help---
		Timer 17 dead-time and sampling clock (t_DTS) division

config STM32H5_TIM17_DEADTIME
	int "TIM17 Initial Dead-time"
	default 0
	range 0 255
	---help---
		Timer 17 initial dead-time

if STM32H5_PWM_MULTICHAN

config STM32H5_TIM17_CHANNEL1
	bool "TIM17 Channel 1"
	default n
	---help---
		Enables channel 1.

if STM32H5_TIM17_CHANNEL1

config STM32H5_TIM17_CH1MODE
	int "TIM17 Channel 1 Mode"
	default 6
	range 0 7
	---help---
		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.

config STM32H5_TIM17_CH1OUT
	bool "TIM17 Channel 1 Output"
	default n
	---help---
		Enables channel 1 output.

endif # STM32H5_TIM17_CHANNEL1

endif # STM32H5_PWM_MULTICHAN

if !STM32H5_PWM_MULTICHAN

config STM32H5_TIM17_CHANNEL
	int "TIM17 PWM Output Channel"
	default 1
	range 1 1
	---help---
		If TIM17 is enabled for PWM usage, you also need specifies the timer output
		channel {1}

if STM32H5_TIM17_CHANNEL = 1

config STM32H5_TIM17_CH1OUT
	bool "TIM17 Channel 1 Output"
	default n
	---help---
		Enables channel 1 output.

endif # STM32H5_TIM17_CHANNEL = 1

config STM32H5_TIM17_CHMODE
	int "TIM17 Channel Mode"
	default 6
	range 0 7
	---help---
		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.

endif # !STM32H5_PWM_MULTICHAN

endif # STM32H5_TIM17_PWM

config STM32H5_PWM_MULTICHAN
	bool "PWM Multiple Output Channels"
	default n
	depends on STM32H5_PWM
	select ARCH_HAVE_PWM_MULTICHAN
	---help---
		Specifies that the PWM driver supports multiple output
		channels per timer.

config STM32H5_TIM1_ADC
	bool "TIM1 ADC"
	default n
	depends on STM32H5_TIM1 && STM32H5_ADC
	---help---
		Reserve timer 1 for use by an ADC

		Timer devices may be used for different purposes.  If STM32H5_TIM1 is
		defined then the following may also be defined to indicate that the
		timer is intended to be used for ADC conversion. Note that ADC usage
		requires two definition:  Not only do you have to assign the timer
		for used by the ADC, but then you also have to configure which ADC
		channel it is assigned to.

choice
	prompt "Select ADC for use with TIM1"
	default STM32H5_TIM1_ADC1
	depends on STM32H5_TIM1_ADC

config STM32H5_TIM1_ADC1
	bool "Use TIM1 for ADC1"
	depends on STM32H5_ADC1
	select STM32H5_HAVE_ADC1_TIMER
	---help---
		Reserve TIM1 to trigger ADC1

config STM32H5_TIM1_ADC2
	bool "Use TIM1 for ADC2"
	depends on STM32H5_ADC2
	select STM32H5_HAVE_ADC2_TIMER
	---help---
		Reserve TIM1 to trigger ADC2

endchoice

config STM32H5_TIM2_ADC
	bool "TIM2 ADC"
	default n
	depends on STM32H5_TIM2 && STM32H5_ADC
	---help---
		Reserve timer 2 for use by an ADC

		Timer devices may be used for different purposes.  If STM32H5_TIM2 is
		defined then the following may also be defined to indicate that the
		timer is intended to be used for ADC conversion. Note that ADC usage
		requires two definition:  Not only do you have to assign the timer
		for used by the ADC, but then you also have to configure which ADC
		channel it is assigned to.

choice
	prompt "Select ADC for use with TIM2"
	default STM32H5_TIM2_ADC1
	depends on STM32H5_TIM2_ADC

config STM32H5_TIM2_ADC1
	bool "Use TIM2 for ADC1"
	depends on STM32H5_ADC1
	select STM32H5_HAVE_ADC1_TIMER
	---help---
		Reserve TIM2 to trigger ADC1

config STM32H5_TIM2_ADC2
	bool "Use TIM2 for ADC2"
	depends on STM32H5_ADC2
	select STM32H5_HAVE_ADC2_TIMER
	---help---
		Reserve TIM2 to trigger ADC2

endchoice

config STM32H5_TIM3_ADC
	bool "TIM3 ADC"
	default n
	depends on STM32H5_TIM3 && STM32H5_ADC
	---help---
		Reserve timer 3 for use by an ADC

		Timer devices may be used for different purposes.  If STM32H5_TIM3 is
		defined then the following may also be defined to indicate that the
		timer is intended to be used for ADC conversion. Note that ADC usage
		requires two definition:  Not only do you have to assign the timer
		for used by the ADC, but then you also have to configure which ADC
		channel it is assigned to.

choice
	prompt "Select ADC for use with TIM3"
	default STM32H5_TIM3_ADC1
	depends on STM32H5_TIM3_ADC

config STM32H5_TIM3_ADC1
	bool "Use TIM3 for ADC1"
	depends on STM32H5_ADC1
	select STM32H5_HAVE_ADC1_TIMER
	---help---
		Reserve TIM3 to trigger ADC1

config STM32H5_TIM3_ADC2
	bool "Use TIM3 for ADC2"
	depends on STM32H5_ADC2
	select STM32H5_HAVE_ADC2_TIMER
	---help---
		Reserve TIM3 to trigger ADC2

endchoice

config STM32H5_TIM4_ADC
	bool "TIM4 ADC"
	default n
	depends on STM32H5_TIM4 && STM32H5_ADC
	---help---
		Reserve timer 4 for use by ADC

		Timer devices may be used for different purposes.  If STM32H5_TIM4 is
		defined then the following may also be defined to indicate that the
		timer is intended to be used for ADC conversion. Note that ADC usage
		requires two definition:  Not only do you have to assign the timer
		for used by the ADC, but then you also have to configure which ADC
		channel it is assigned to.

choice
	prompt "Select ADC for use with TIM4"
	default STM32H5_TIM4_ADC1
	depends on STM32H5_TIM4_ADC

config STM32H5_TIM4_ADC1
	bool "Use TIM4 for ADC1"
	depends on STM32H5_ADC1
	select STM32H5_HAVE_ADC1_TIMER
	---help---
		Reserve TIM4 to trigger ADC1

config STM32H5_TIM4_ADC2
	bool "Use TIM4 for ADC2"
	depends on STM32H5_ADC2
	select STM32H5_HAVE_ADC2_TIMER
	---help---
		Reserve TIM4 to trigger ADC2

endchoice

config STM32H5_TIM6_ADC
	bool "TIM6 ADC"
	default n
	depends on STM32H5_TIM6 && STM32H5_ADC
	---help---
		Reserve timer 6 for use by ADC

		Timer devices may be used for different purposes.  If STM32H5_TIM6 is
		defined then the following may also be defined to indicate that the
		timer is intended to be used for ADC conversion. Note that ADC usage
		requires two definition:  Not only do you have to assign the timer
		for used by the ADC, but then you also have to configure which ADC
		channel it is assigned to.

choice
	prompt "Select ADC for use with TIM6"
	default STM32H5_TIM6_ADC1
	depends on STM32H5_TIM6_ADC

config STM32H5_TIM6_ADC1
	bool "Use TIM6 for ADC1"
	depends on STM32H5_ADC1
	select STM32H5_HAVE_ADC1_TIMER
	---help---
		Reserve TIM6 to trigger ADC1

config STM32H5_TIM6_ADC2
	bool "Use TIM6 for ADC2"
	depends on STM32H5_ADC2
	select STM32H5_HAVE_ADC2_TIMER
	---help---
		Reserve TIM6 to trigger ADC2

endchoice

config STM32H5_TIM8_ADC
	bool "TIM8 ADC"
	default n
	depends on STM32H5_TIM8 && STM32H5_ADC
	---help---
		Reserve timer 8 for use by ADC

		Timer devices may be used for different purposes.  If STM32H5_TIM8 is
		defined then the following may also be defined to indicate that the
		timer is intended to be used for ADC conversion. Note that ADC usage
		requires two definition:  Not only do you have to assign the timer
		for used by the ADC, but then you also have to configure which ADC
		channel it is assigned to.

choice
	prompt "Select ADC for use with TIM8"
	default STM32H5_TIM8_ADC1
	depends on STM32H5_TIM8_ADC

config STM32H5_TIM8_ADC1
	bool "Use TIM8 for ADC1"
	depends on STM32H5_ADC1
	select STM32H5_HAVE_ADC1_TIMER
	---help---
		Reserve TIM8 to trigger ADC1

config STM32H5_TIM8_ADC2
	bool "Use TIM8 for ADC2"
	depends on STM32H5_ADC2
	select STM32H5_HAVE_ADC2_TIMER
	---help---
		Reserve TIM8 to trigger ADC2

endchoice

config STM32H5_TIM15_ADC
	bool "TIM15 ADC"
	default n
	depends on STM32H5_TIM15 && STM32H5_ADC
	---help---
		Reserve timer 15 for use by ADC

		Timer devices may be used for different purposes.  If STM32H5_TIM15 is
		defined then the following may also be defined to indicate that the
		timer is intended to be used for ADC conversion. Note that ADC usage
		requires two definition:  Not only do you have to assign the timer
		for used by the ADC, but then you also have to configure which ADC
		channel it is assigned to.

choice
	prompt "Select ADC for use with TIM15"
	default STM32H5_TIM15_ADC1
	depends on STM32H5_TIM15_ADC

config STM32H5_TIM15_ADC1
	bool "Use TIM15 for ADC1"
	depends on STM32H5_ADC1
	select STM32H5_HAVE_ADC1_TIMER
	---help---
		Reserve TIM15 to trigger ADC1

config STM32H5_TIM15_ADC2
	bool "Use TIM15 for ADC2"
	depends on STM32H5_ADC2
	select STM32H5_HAVE_ADC2_TIMER
	---help---
		Reserve TIM15 to trigger ADC2

endchoice

config STM32H5_HAVE_ADC1_TIMER
	bool

config STM32H5_HAVE_ADC2_TIMER
	bool

config STM32H5_ADC1_SAMPLE_FREQUENCY
	int "ADC1 Sampling Frequency"
	default 100
	depends on STM32H5_HAVE_ADC1_TIMER
	---help---
		ADC1 sampling frequency.  Default:  100Hz

config STM32H5_ADC1_TIMTRIG
	int "ADC1 Timer Trigger"
	default 0
	range 0 5
	depends on STM32H5_HAVE_ADC1_TIMER
	---help---
		Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2

config STM32H5_ADC2_SAMPLE_FREQUENCY
	int "ADC2 Sampling Frequency"
	default 100
	depends on STM32H5_HAVE_ADC2_TIMER
	---help---
		ADC2 sampling frequency.  Default:  100Hz

config STM32H5_ADC2_TIMTRIG
	int "ADC2 Timer Trigger"
	default 0
	range 0 5
	depends on STM32H5_HAVE_ADC2_TIMER
	---help---
		Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2

config STM32H5_TIM1_CAP
	bool "TIM1 Capture"
	default n
	depends on STM32H5_TIM1
	---help---
		Reserve timer 1 for use by Capture

		Timer devices may be used for different purposes.  One special purpose is
		to capture input.

config STM32H5_TIM2_CAP
	bool "TIM2 Capture"
	default n
	depends on STM32H5_TIM2
	---help---
		Reserve timer 2 for use by Capture

		Timer devices may be used for different purposes.  One special purpose is
		to capture input.

config STM32H5_TIM3_CAP
	bool "TIM3 Capture"
	default n
	depends on STM32H5_TIM3
	---help---
		Reserve timer 3 for use by Capture

		Timer devices may be used for different purposes.  One special purpose is
		to capture input.

config STM32H5_TIM4_CAP
	bool "TIM4 Capture"
	default n
	depends on STM32H5_TIM4
	---help---
		Reserve timer 4 for use by Capture

		Timer devices may be used for different purposes.  One special purpose is
		to capture input.

config STM32H5_TIM5_CAP
	bool "TIM5 Capture"
	default n
	depends on STM32H5_TIM5
	---help---
		Reserve timer 5 for use by Capture

		Timer devices may be used for different purposes.  One special purpose is
		to capture input.

config STM32H5_TIM8_CAP
	bool "TIM8 Capture"
	default n
	depends on STM32H5_TIM8
	---help---
		Reserve timer 8 for use by Capture

		Timer devices may be used for different purposes.  One special purpose is
		to capture input.

config STM32H5_TIM12_CAP
	bool "TIM12 Capture"
	default n
	depends on STM32H5_TIM12
	---help---
		Reserve timer 12 for use by Capture

		Timer devices may be used for different purposes.  One special purpose is
		to capture input.

config STM32H5_TIM13_CAP
	bool "TIM13 Capture"
	default n
	depends on STM32H5_TIM13
	---help---
		Reserve timer 13 for use by Capture

		Timer devices may be used for different purposes.  One special purpose is
		to capture input.

config STM32H5_TIM14_CAP
	bool "TIM14 Capture"
	default n
	depends on STM32H5_TIM14
	---help---
		Reserve timer 14 for use by Capture

		Timer devices may be used for different purposes.  One special purpose is
		to capture input.

config STM32H5_TIM15_CAP
	bool "TIM15 Capture"
	default n
	depends on STM32H5_TIM15
	---help---
		Reserve timer 15 for use by Capture

		Timer devices may be used for different purposes.  One special purpose is
		to capture input.

config STM32H5_TIM16_CAP
	bool "TIM16 Capture"
	default n
	depends on STM32H5_TIM16
	---help---
		Reserve timer 16 for use by Capture

		Timer devices may be used for different purposes.  One special purpose is
		to capture input.

config STM32H5_TIM17_CAP
	bool "TIM14 Capture"
	default n
	depends on STM32H5_TIM17
	---help---
		Reserve timer 17 for use by Capture

		Timer devices may be used for different purposes.  One special purpose is
		to capture input.

menu "STM32 TIMx Outputs Configuration"

config STM32H5_TIM1_CH1POL
	int "TIM1 Channel 1 Output polarity"
	default 0
	range 0 1
	depends on STM32H5_TIM1_CH1OUT
	---help---
		TIM1 Channel 1 output polarity

config STM32H5_TIM1_CH1IDLE
	int "TIM1 Channel 1 Output IDLE"
	default 0
	range 0 1
	depends on STM32H5_TIM1_CH1OUT
	---help---
		TIM1 Channel 1 output IDLE

config STM32H5_TIM1_CH1NPOL
	int "TIM1 Channel 1 Complementary Output polarity"
	default 0
	range 0 1
	depends on STM32H5_TIM1_CH1NOUT
	---help---
		TIM1 Channel 1 Complementary Output polarity

config STM32H5_TIM1_CH1NIDLE
	int "TIM1 Channel 1 Complementary Output IDLE"
	default 0
	range 0 1
	depends on STM32H5_TIM1_CH1NOUT
	---help---
		TIM1 Channel 1 Complementary Output IDLE

config STM32H5_TIM1_CH2POL
	int "TIM1 Channel 2 Output polarity"
	default 0
	range 0 1
	depends on STM32H5_TIM1_CH2OUT
	---help---
		TIM1 Channel 2 output polarity

config STM32H5_TIM1_CH2IDLE
	int "TIM1 Channel 2 Output IDLE"
	default 0
	range 0 1
	depends on STM32H5_TIM1_CH2OUT
	---help---
		TIM1 Channel 2 output IDLE

config STM32H5_TIM1_CH2NPOL
	int "TIM1 Channel 2 Complementary Output polarity"
	default 0
	range 0 1
	depends on STM32H5_TIM1_CH2NOUT
	---help---
		TIM1 Channel 2 Complementary Output polarity

config STM32H5_TIM1_CH2NIDLE
	int "TIM1 Channel 2 Complementary Output IDLE"
	default 0
	range 0 1
	depends on STM32H5_TIM1_CH2NOUT
	---help---
		TIM1 Channel 2 Complementary Output IDLE

config STM32H5_TIM1_CH3POL
	int "TIM1 Channel 3 Output polarity"
	default 0
	range 0 1
	depends on STM32H5_TIM1_CH3OUT
	---help---
		TIM1 Channel 3 output polarity

config STM32H5_TIM1_CH3IDLE
	int "TIM1 Channel 3 Output IDLE"
	default 0
	range 0 1
	depends on STM32H5_TIM1_CH3OUT
	---help---
		TIM1 Channel 3 output IDLE

config STM32H5_TIM1_CH3NPOL
	int "TIM1 Channel 3 Complementary Output polarity"
	default 0
	range 0 1
	depends on STM32H5_TIM1_CH3NOUT
	---help---
		TIM1 Channel 3 Complementary Output polarity

config STM32H5_TIM1_CH3NIDLE
	int "TIM1 Channel 3 Complementary Output IDLE"
	default 0
	range 0 1
	depends on STM32H5_TIM1_CH3NOUT
	---help---
		TIM1 Channel 3 Complementary Output IDLE

config STM32H5_TIM1_CH4POL
	int "TIM1 Channel 4 Output polarity"
	default 0
	range 0 1
	depends on STM32H5_TIM1_CH4OUT
	---help---
		TIM1 Channel 4 output polarity

config STM32H5_TIM1_CH4IDLE
	int "TIM1 Channel 4 Output IDLE"
	default 0
	range 0 1
	depends on STM32H5_TIM1_CH4OUT
	---help---
		TIM1 Channel 4 output IDLE

config STM32H5_TIM1_CH5POL
	int "TIM1 Channel 5 Output polarity"
	default 0
	range 0 1
	depends on STM32H5_TIM1_CH5OUT
	---help---
		TIM1 Channel 5 output polarity

config STM32H5_TIM1_CH5IDLE
	int "TIM1 Channel 5 Output IDLE"
	default 0
	range 0 1
	depends on STM32H5_TIM1_CH5OUT
	---help---
		TIM1 Channel 5 output IDLE

config STM32H5_TIM1_CH6POL
	int "TIM1 Channel 6 Output polarity"
	default 0
	range 0 1
	depends on STM32H5_TIM1_CH6OUT
	---help---
		TIM1 Channel 6 output polarity

config STM32H5_TIM1_CH6IDLE
	int "TIM1 Channel 6 Output IDLE"
	default 0
	range 0 1
	depends on STM32H5_TIM1_CH6OUT
	---help---
		TIM1 Channel 6 output IDLE

config STM32H5_TIM2_CH1POL
	int "TIM2 Channel 1 Output polarity"
	default 0
	range 0 1
	depends on STM32H5_TIM2_CH1OUT
	---help---
		TIM2 Channel 1 output polarity

config STM32H5_TIM2_CH1IDLE
	int "TIM2 Channel 1 Output IDLE"
	default 0
	range 0 1
	depends on STM32H5_TIM2_CH1OUT
	---help---
		TIM2 Channel 1 output IDLE

config STM32H5_TIM2_CH2POL
	int "TIM2 Channel 2 Output polarity"
	default 0
	range 0 1
	depends on STM32H5_TIM2_CH2OUT
	---help---
		TIM2 Channel 2 output polarity

config STM32H5_TIM2_CH2IDLE
	int "TIM2 Channel 2 Output IDLE"
	default 0
	range 0 1
	depends on STM32H5_TIM2_CH2OUT
	---help---
		TIM2 Channel 2 output IDLE

config STM32H5_TIM2_CH3POL
	int "TIM2 Channel 3 Output polarity"
	default 0
	range 0 1
	depends on STM32H5_TIM2_CH3OUT
	---help---
		TIM2 Channel 3 output polarity

config STM32H5_TIM2_CH3IDLE
	int "TIM2 Channel 3 Output IDLE"
	default 0
	range 0 1
	depends on STM32H5_TIM2_CH3OUT
	---help---
		TIM2 Channel 3 output IDLE

config STM32H5_TIM2_CH4POL
	int "TIM2 Channel 4 Output polarity"
	default 0
	range 0 1
	depends on STM32H5_TIM2_CH4OUT
	---help---
		TIM2 Channel 4 output polarity

config STM32H5_TIM2_CH4IDLE
	int "TIM2 Channel 4 Output IDLE"
	default 0
	range 0 1
	depends on STM32H5_TIM2_CH4OUT
	---help---
		TIM2 Channel 4 output IDLE

config STM32H5_TIM3_CH1POL
	int "TIM3 Channel 1 Output polarity"
	default 0
	range 0 1
	depends on STM32H5_TIM3_CH1OUT
	---help---
		TIM3 Channel 1 output polarity

config STM32H5_TIM3_CH1IDLE
	int "TIM3 Channel 1 Output IDLE"
	default 0
	range 0 1
	depends on STM32H5_TIM3_CH1OUT
	---help---
		TIM3 Channel 1 output IDLE

config STM32H5_TIM3_CH2POL
	int "TIM3 Channel 2 Output polarity"
	default 0
	range 0 1
	depends on STM32H5_TIM3_CH2OUT
	---help---
		TIM3 Channel 2 output polarity

config STM32H5_TIM3_CH2IDLE
	int "TIM3 Channel 2 Output IDLE"
	default 0
	range 0 1
	depends on STM32H5_TIM3_CH2OUT
	---help---
		TIM3 Channel 2 output IDLE

config STM32H5_TIM3_CH3POL
	int "TIM3 Channel 3 Output polarity"
	default 0
	range 0 1
	depends on STM32H5_TIM3_CH3OUT
	---help---
		TIM3 Channel 3 output polarity

config STM32H5_TIM3_CH3IDLE
	int "TIM3 Channel 3 Output IDLE"
	default 0
	range 0 1
	depends on STM32H5_TIM3_CH3OUT
	---help---
		TIM3 Channel 3 output IDLE

config STM32H5_TIM3_CH4POL
	int "TIM3 Channel 4 Output polarity"
	default 0
	range 0 1
	depends on STM32H5_TIM3_CH4OUT
	---help---
		TIM3 Channel 4 output polarity

config STM32H5_TIM3_CH4IDLE
	int "TIM3 Channel 4 Output IDLE"
	default 0
	range 0 1
	depends on STM32H5_TIM3_CH4OUT
	---help---
		TIM3 Channel 4 output IDLE

config STM32H5_TIM4_CH1POL
	int "TIM4 Channel 1 Output polarity"
	default 0
	range 0 1
	depends on STM32H5_TIM4_CH1OUT
	---help---
		TIM4 Channel 1 output polarity

config STM32H5_TIM4_CH1IDLE
	int "TIM4 Channel 1 Output IDLE"
	default 0
	range 0 1
	depends on STM32H5_TIM4_CH1OUT
	---help---
		TIM4 Channel 1 output IDLE

config STM32H5_TIM4_CH2POL
	int "TIM4 Channel 2 Output polarity"
	default 0
	range 0 1
	depends on STM32H5_TIM4_CH2OUT
	---help---
		TIM4 Channel 2 output polarity

config STM32H5_TIM4_CH2IDLE
	int "TIM4 Channel 2 Output IDLE"
	default 0
	range 0 1
	depends on STM32H5_TIM4_CH2OUT
	---help---
		TIM4 Channel 2 output IDLE

config STM32H5_TIM4_CH3POL
	int "TIM4 Channel 3 Output polarity"
	default 0
	range 0 1
	depends on STM32H5_TIM4_CH3OUT
	---help---
		TIM4 Channel 3 output polarity

config STM32H5_TIM4_CH3IDLE
	int "TIM4 Channel 3 Output IDLE"
	default 0
	range 0 1
	depends on STM32H5_TIM4_CH3OUT
	---help---
		TIM4 Channel 3 output IDLE

config STM32H5_TIM4_CH4POL
	int "TIM4 Channel 4 Output polarity"
	default 0
	range 0 1
	depends on STM32H5_TIM4_CH4OUT
	---help---
		TIM4 Channel 4 output polarity

config STM32H5_TIM4_CH4IDLE
	int "TIM4 Channel 4 Output IDLE"
	default 0
	range 0 1
	depends on STM32H5_TIM4_CH4OUT
	---help---
		TIM4 Channel 4 output IDLE

config STM32H5_TIM5_CH1POL
	int "TIM5 Channel 1 Output polarity"
	default 0
	range 0 1
	depends on STM32H5_TIM5_CH1OUT
	---help---
		TIM5 Channel 1 output polarity

config STM32H5_TIM5_CH1IDLE
	int "TIM5 Channel 1 Output IDLE"
	default 0
	range 0 1
	depends on STM32H5_TIM5_CH1OUT
	---help---
		TIM5 Channel 1 output IDLE

config STM32H5_TIM5_CH2POL
	int "TIM5 Channel 2 Output polarity"
	default 0
	range 0 1
	depends on STM32H5_TIM5_CH2OUT
	---help---
		TIM5 Channel 2 output polarity

config STM32H5_TIM5_CH2IDLE
	int "TIM5 Channel 2 Output IDLE"
	default 0
	range 0 1
	depends on STM32H5_TIM5_CH2OUT
	---help---
		TIM5 Channel 2 output IDLE

config STM32H5_TIM5_CH3POL
	int "TIM5 Channel 3 Output polarity"
	default 0
	range 0 1
	depends on STM32H5_TIM5_CH3OUT
	---help---
		TIM5 Channel 3 output polarity

config STM32H5_TIM5_CH3IDLE
	int "TIM5 Channel 3 Output IDLE"
	default 0
	range 0 1
	depends on STM32H5_TIM5_CH3OUT
	---help---
		TIM5 Channel 3 output IDLE

config STM32H5_TIM5_CH4POL
	int "TIM5 Channel 4 Output polarity"
	default 0
	range 0 1
	depends on STM32H5_TIM5_CH4OUT
	---help---
		TIM5 Channel 4 output polarity

config STM32H5_TIM5_CH4IDLE
	int "TIM5 Channel 4 Output IDLE"
	default 0
	range 0 1
	depends on STM32H5_TIM5_CH4OUT
	---help---
		TIM5 Channel 4 output IDLE

config STM32H5_TIM8_CH1POL
	int "TIM8 Channel 1 Output polarity"
	default 0
	range 0 1
	depends on STM32H5_TIM8_CH1OUT
	---help---
		TIM8 Channel 1 output polarity

config STM32H5_TIM8_CH1IDLE
	int "TIM8 Channel 1 Output IDLE"
	default 0
	range 0 1
	depends on STM32H5_TIM8_CH1OUT
	---help---
		TIM8 Channel 1 output IDLE

config STM32H5_TIM8_CH1NPOL
	int "TIM8 Channel 1 Complementary Output polarity"
	default 0
	range 0 1
	depends on STM32H5_TIM8_CH1NOUT
	---help---
		TIM8 Channel 1 Complementary Output polarity

config STM32H5_TIM8_CH1NIDLE
	int "TIM8 Channel 1 Complementary Output IDLE"
	default 0
	range 0 1
	depends on STM32H5_TIM8_CH1NOUT
	---help---
		TIM8 Channel 1 Complementary Output IDLE

config STM32H5_TIM8_CH2POL
	int "TIM8 Channel 2 Output polarity"
	default 0
	range 0 1
	depends on STM32H5_TIM8_CH2OUT
	---help---
		TIM8 Channel 2 output polarity

config STM32H5_TIM8_CH2IDLE
	int "TIM8 Channel 2 Output IDLE"
	default 0
	range 0 1
	depends on STM32H5_TIM8_CH2OUT
	---help---
		TIM8 Channel 2 output IDLE

config STM32H5_TIM8_CH2NPOL
	int "TIM8 Channel 2 Complementary Output polarity"
	default 0
	range 0 1
	depends on STM32H5_TIM8_CH2NOUT
	---help---
		TIM8 Channel 2 Complementary Output polarity

config STM32H5_TIM8_CH2NIDLE
	int "TIM8 Channel 2 Complementary Output IDLE"
	default 0
	range 0 1
	depends on STM32H5_TIM8_CH2NOUT
	---help---
		TIM8 Channel 2 Complementary Output IDLE

config STM32H5_TIM8_CH3POL
	int "TIM8 Channel 3 Output polarity"
	default 0
	range 0 1
	depends on STM32H5_TIM8_CH3OUT
	---help---
		TIM8 Channel 3 output polarity

config STM32H5_TIM8_CH3IDLE
	int "TIM8 Channel 3 Output IDLE"
	default 0
	range 0 1
	depends on STM32H5_TIM8_CH3OUT
	---help---
		TIM8 Channel 3 output IDLE

config STM32H5_TIM8_CH3NPOL
	int "TIM8 Channel 3 Complementary Output polarity"
	default 0
	range 0 1
	depends on STM32H5_TIM8_CH3NOUT
	---help---
		TIM8 Channel 3 Complementary Output polarity

config STM32H5_TIM8_CH3NIDLE
	int "TIM8 Channel 3 Complementary Output IDLE"
	default 0
	range 0 1
	depends on STM32H5_TIM8_CH3NOUT
	---help---
		TIM8 Channel 3 Complementary Output IDLE

config STM32H5_TIM8_CH4POL
	int "TIM8 Channel 4 Output polarity"
	default 0
	range 0 1
	depends on STM32H5_TIM8_CH4OUT
	---help---
		TIM8 Channel 4 output polarity

config STM32H5_TIM8_CH4IDLE
	int "TIM8 Channel 4 Output IDLE"
	default 0
	range 0 1
	depends on STM32H5_TIM8_CH4OUT
	---help---
		TIM8 Channel 4 output IDLE

config STM32H5_TIM8_CH5POL
	int "TIM8 Channel 5 Output polarity"
	default 0
	range 0 1
	depends on STM32H5_TIM8_CH5OUT
	---help---
		TIM8 Channel 5 output polarity

config STM32H5_TIM8_CH5IDLE
	int "TIM8 Channel 5 Output IDLE"
	default 0
	range 0 1
	depends on STM32H5_TIM8_CH5OUT
	---help---
		TIM8 Channel 5 output IDLE

config STM32H5_TIM8_CH6POL
	int "TIM8 Channel 6 Output polarity"
	default 0
	range 0 1
	depends on STM32H5_TIM8_CH6OUT
	---help---
		TIM8 Channel 6 output polarity

config STM32H5_TIM8_CH6IDLE
	int "TIM8 Channel 6 Output IDLE"
	default 0
	range 0 1
	depends on STM32H5_TIM8_CH6OUT
	---help---
		TIM8 Channel 6 output IDLE

config STM32H5_TIM12_CH1POL
	int "TIM12 Channel 1 Output polarity"
	default 0
	range 0 1
	depends on STM32H5_TIM12_CH1OUT
	---help---
		TIM12 Channel 1 output polarity

config STM32H5_TIM12_CH1IDLE
	int "TIM12 Channel 1 Output IDLE"
	default 0
	range 0 1
	depends on STM32H5_TIM12_CH1OUT
	---help---
		TIM12 Channel 1 output IDLE

config STM32H5_TIM12_CH2POL
	int "TIM12 Channel 2 Output polarity"
	default 0
	range 0 1
	depends on STM32H5_TIM12_CH2OUT
	---help---
		TIM12 Channel 2 output polarity

config STM32H5_TIM12_CH2IDLE
	int "TIM12 Channel 2 Output IDLE"
	default 0
	range 0 1
	depends on STM32H5_TIM12_CH2OUT
	---help---
		TIM12 Channel 2 output IDLE

config STM32H5_TIM13_CH1POL
	int "TIM13 Channel 1 Output polarity"
	default 0
	range 0 1
	depends on STM32H5_TIM13_CH1OUT
	---help---
		TIM13 Channel 1 output polarity

config STM32H5_TIM13_CH1IDLE
	int "TIM13 Channel 1 Output IDLE"
	default 0
	range 0 1
	depends on STM32H5_TIM13_CH1OUT
	---help---
		TIM13 Channel 1 output IDLE

config STM32H5_TIM14_CH1POL
	int "TIM14 Channel 1 Output polarity"
	default 0
	range 0 1
	depends on STM32H5_TIM14_CH1OUT
	---help---
		TIM14 Channel 1 output polarity

config STM32H5_TIM14_CH1IDLE
	int "TIM14 Channel 1 Output IDLE"
	default 0
	range 0 1
	depends on STM32H5_TIM14_CH1OUT
	---help---
		TIM14 Channel 1 output IDLE

config STM32H5_TIM15_CH1POL
	int "TIM15 Channel 1 Output polarity"
	default 0
	range 0 1
	depends on STM32H5_TIM15_CH1OUT
	---help---
		TIM15 Channel 1 output polarity

config STM32H5_TIM15_CH1IDLE
	int "TIM15 Channel 1 Output IDLE"
	default 0
	range 0 1
	depends on STM32H5_TIM15_CH1OUT
	---help---
		TIM15 Channel 1 output IDLE

config STM32H5_TIM15_CH1NPOL
	int "TIM15 Channel 1 Complementary Output polarity"
	default 0
	range 0 1
	depends on STM32H5_TIM15_CH1NOUT
	---help---
		TIM15 Channel 1 Complementary Output polarity

config STM32H5_TIM15_CH1NIDLE
	int "TIM15 Channel 1 Complementary Output IDLE"
	default 0
	range 0 1
	depends on STM32H5_TIM15_CH1NOUT
	---help---
		TIM15 Channel 1 Complementary Output IDLE

config STM32H5_TIM15_CH2POL
	int "TIM15 Channel 2 Output polarity"
	default 0
	range 0 1
	depends on STM32H5_TIM15_CH2OUT
	---help---
		TIM15 Channel 2 output polarity

config STM32H5_TIM15_CH2IDLE
	int "TIM15 Channel 2 Output IDLE"
	default 0
	range 0 1
	depends on STM32H5_TIM15_CH2OUT
	---help---
		TIM15 Channel 2 output IDLE

config STM32H5_TIM15_CH2NPOL
	int "TIM15 Channel 2 Complementary Output polarity"
	default 0
	range 0 1
	depends on STM32H5_TIM15_CH2NOUT
	---help---
		TIM15 Channel 2 Complementary Output polarity

config STM32H5_TIM15_CH2NIDLE
	int "TIM15 Channel 2 Complementary Output IDLE"
	default 0
	range 0 1
	depends on STM32H5_TIM15_CH2NOUT
	---help---
		TIM15 Channel 2 Complementary Output IDLE

config STM32H5_TIM16_CH1POL
	int "TIM16 Channel 1 Output polarity"
	default 0
	range 0 1
	depends on STM32H5_TIM16_CH1OUT
	---help---
		TIM16 Channel 1 output polarity

config STM32H5_TIM16_CH1IDLE
	int "TIM16 Channel 1 Output IDLE"
	default 0
	range 0 1
	depends on STM32H5_TIM16_CH1OUT
	---help---
		TIM16 Channel 1 output IDLE

config STM32H5_TIM17_CH1POL
	int "TIM17 Channel 1 Output polarity"
	default 0
	range 0 1
	depends on STM32H5_TIM17_CH1OUT
	---help---
		TIM17 Channel 1 output polarity

config STM32H5_TIM17_CH1IDLE
	int "TIM17 Channel 1 Output IDLE"
	default 0
	range 0 1
	depends on STM32H5_TIM17_CH1OUT
	---help---
		TIM17 Channel 1 output IDLE

endmenu #STM32 TIMx Outputs Configuration

endmenu # Timer Configuration

comment "USB Device Configuration"

menu "USB Full Speed Debug Configuration"
	depends on STM32H5_USBFS

config STM32H5_USBFS_REGDEBUG
	bool "Register-Level Debug"
	default n
	depends on STM32H5_USBFS && DEBUG_USB_INFO
	---help---
		Enable very low-level register access debug.

endmenu

config STM32H5_SERIALDRIVER
	bool

menu "[LP]U[S]ART Configuration"
	depends on STM32H5_USART

choice
	prompt "LPUART1 Driver Configuration"
	default STM32H5_LPUART1_SERIALDRIVER
	depends on STM32H5_LPUART1

config STM32H5_LPUART1_SERIALDRIVER
	bool "Standard serial driver"
	select LPUART1_SERIALDRIVER
	select STM32H5_SERIALDRIVER

endchoice # LPUART1 Driver Configuration

if LPUART1_SERIALDRIVER

config LPUART1_RS485
	bool "RS-485 on LPUART1"
	default n
	depends on STM32H5_LPUART1
	---help---
		Enable RS-485 interface on LPUART1. Your board config will have to
		provide GPIO_LPUART1_RS485_DIR pin definition. Currently it cannot be
		used with LPUART1_RXDMA.

config LPUART1_RS485_DIR_POLARITY
	int "LPUART1 RS-485 DIR pin polarity"
	default 1
	range 0 1
	depends on LPUART1_RS485
	---help---
		Polarity of DIR pin for RS-485 on LPUART1. Set to state on DIR pin which
		enables TX (0 - low / nTXEN, 1 - high / TXEN).

config LPUART1_RXDMA
	bool "LPUART1 RX DMA"
	default n
	depends on STM32H5_LPUART1 && (STM32H5_DMA1 || STM32H5_DMA2)
	---help---
		In high data rate usage, Rx DMA may eliminate Rx overrun errors

endif # LPUART1_SERIALDRIVER

choice
	prompt "USART1 Driver Configuration"
	default STM32H5_USART1_SERIALDRIVER
	depends on STM32H5_USART1

config STM32H5_USART1_SERIALDRIVER
	bool "Standard serial driver"
	select USART1_SERIALDRIVER
	select STM32H5_SERIALDRIVER

endchoice # USART1 Driver Configuration

if USART1_SERIALDRIVER

config USART1_RS485
	bool "RS-485 on USART1"
	default n
	depends on STM32H5_USART1
	---help---
		Enable RS-485 interface on USART1. Your board config will have to
		provide GPIO_USART1_RS485_DIR pin definition. Currently it cannot be
		used with USART1_RXDMA.

config USART1_RS485_DIR_POLARITY
	int "USART1 RS-485 DIR pin polarity"
	default 1
	range 0 1
	depends on USART1_RS485
	---help---
		Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which
		enables TX (0 - low / nTXEN, 1 - high / TXEN).

config USART1_RXDMA
	bool "USART1 RX DMA"
	default n
	depends on STM32H5_USART1 && (STM32H5_DMA1 || STM32H5_DMA2)
	---help---
		In high data rate usage, Rx DMA may eliminate Rx overrun errors

endif # USART1_SERIALDRIVER

choice
	prompt "USART2 Driver Configuration"
	default STM32H5_USART2_SERIALDRIVER
	depends on STM32H5_USART2

config STM32H5_USART2_SERIALDRIVER
	bool "Standard serial driver"
	select USART2_SERIALDRIVER
	select STM32H5_SERIALDRIVER

endchoice # USART2 Driver Configuration

if USART2_SERIALDRIVER

config USART2_RS485
	bool "RS-485 on USART2"
	default n
	depends on STM32H5_USART2
	---help---
		Enable RS-485 interface on USART2. Your board config will have to
		provide GPIO_USART2_RS485_DIR pin definition. Currently it cannot be
		used with USART2_RXDMA.

config USART2_RS485_DIR_POLARITY
	int "USART2 RS-485 DIR pin polarity"
	default 1
	range 0 1
	depends on USART2_RS485
	---help---
		Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which
		enables TX (0 - low / nTXEN, 1 - high / TXEN).

config USART2_RXDMA
	bool "USART2 RX DMA"
	default n
	depends on STM32H5_USART2 && (STM32H5_DMA1 || STM32H5_DMA2)
	---help---
		In high data rate usage, Rx DMA may eliminate Rx overrun errors

endif # USART2_SERIALDRIVER

choice
	prompt "USART3 Driver Configuration"
	default STM32H5_USART3_SERIALDRIVER
	depends on STM32H5_USART3

config STM32H5_USART3_SERIALDRIVER
	bool "Standard serial driver"
	select USART3_SERIALDRIVER
	select STM32H5_SERIALDRIVER

endchoice # USART3 Driver Configuration

if USART3_SERIALDRIVER

config USART3_RS485
	bool "RS-485 on USART3"
	default n
	depends on STM32H5_USART3
	---help---
		Enable RS-485 interface on USART3. Your board config will have to
		provide GPIO_USART3_RS485_DIR pin definition. Currently it cannot be
		used with USART3_RXDMA.

config USART3_RS485_DIR_POLARITY
	int "USART3 RS-485 DIR pin polarity"
	default 1
	range 0 1
	depends on USART3_RS485
	---help---
		Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which
		enables TX (0 - low / nTXEN, 1 - high / TXEN).

config USART3_RXDMA
	bool "USART3 RX DMA"
	default n
	depends on STM32H5_USART3 && (STM32H5_DMA1 || STM32H5_DMA2)
	---help---
		In high data rate usage, Rx DMA may eliminate Rx overrun errors

endif # USART3_SERIALDRIVER

choice
	prompt "UART4 Driver Configuration"
	default STM32H5_UART4_SERIALDRIVER
	depends on STM32H5_UART4

config STM32H5_UART4_SERIALDRIVER
	bool "Standard serial driver"
	select UART4_SERIALDRIVER
	select STM32H5_SERIALDRIVER

endchoice # UART4 Driver Configuration

if UART4_SERIALDRIVER

config UART4_RS485
	bool "RS-485 on UART4"
	default n
	depends on STM32H5_UART4
	---help---
		Enable RS-485 interface on UART4. Your board config will have to
		provide GPIO_UART4_RS485_DIR pin definition. Currently it cannot be
		used with UART4_RXDMA.

config UART4_RS485_DIR_POLARITY
	int "UART4 RS-485 DIR pin polarity"
	default 1
	range 0 1
	depends on UART4_RS485
	---help---
		Polarity of DIR pin for RS-485 on UART4. Set to state on DIR pin which
		enables TX (0 - low / nTXEN, 1 - high / TXEN).

config UART4_RXDMA
	bool "UART4 RX DMA"
	default n
	depends on STM32H5_UART4 && (STM32H5_DMA1 || STM32H5_DMA2)
	---help---
		In high data rate usage, Rx DMA may eliminate Rx overrun errors

endif # UART4_SERIALDRIVER

choice
	prompt "UART5 Driver Configuration"
	default STM32H5_UART5_SERIALDRIVER
	depends on STM32H5_UART5

config STM32H5_UART5_SERIALDRIVER
	bool "Standard serial driver"
	select UART5_SERIALDRIVER
	select STM32H5_SERIALDRIVER

endchoice # UART5 Driver Configuration

if UART5_SERIALDRIVER

config UART5_RS485
	bool "RS-485 on UART5"
	default n
	depends on STM32H5_UART5
	---help---
		Enable RS-485 interface on UART5. Your board config will have to
		provide GPIO_UART5_RS485_DIR pin definition. Currently it cannot be
		used with UART5_RXDMA.

config UART5_RS485_DIR_POLARITY
	int "UART5 RS-485 DIR pin polarity"
	default 1
	range 0 1
	depends on UART5_RS485
	---help---
		Polarity of DIR pin for RS-485 on UART5. Set to state on DIR pin which
		enables TX (0 - low / nTXEN, 1 - high / TXEN).

config UART5_RXDMA
	bool "UART5 RX DMA"
	default n
	depends on STM32H5_UART5 && (STM32H5_DMA1 || STM32H5_DMA2)
	---help---
		In high data rate usage, Rx DMA may eliminate Rx overrun errors

endif # UART5_SERIALDRIVER

choice
	prompt "USART6 Driver Configuration"
	default STM32H5_USART6_SERIALDRIVER
	depends on STM32H5_USART6

config STM32H5_USART6_SERIALDRIVER
	bool "Standard serial driver"
	select USART6_SERIALDRIVER
	select STM32H5_SERIALDRIVER

endchoice # USART6 Driver Configuration

if USART6_SERIALDRIVER

config USART6_RS485
	bool "RS-485 on USART6"
	default n
	depends on STM32H5_USART6
	---help---
		Enable RS-485 interface on USART6. Your board config will have to
		provide GPIO_USART6_RS485_DIR pin definition. Currently it cannot be
		used with USART6_RXDMA.

config USART6_RS485_DIR_POLARITY
	int "USART6 RS-485 DIR pin polarity"
	default 1
	range 0 1
	depends on USART6_RS485
	---help---
		Polarity of DIR pin for RS-485 on USART6. Set to state on DIR pin which
		enables TX (0 - low / nTXEN, 1 - high / TXEN).

config USART6_RXDMA
	bool "USART6 RX DMA"
	default n
	depends on STM32H5_USART6 && (STM32H5_DMA1 || STM32H5_DMA2)
	---help---
		In high data rate usage, Rx DMA may eliminate Rx overrun errors

endif # USART6_SERIALDRIVER

if UART7_SERIALDRIVER

config UART7_RS485
	bool "RS-485 on UART7"
	default n
	depends on STM32H5_UART7
	---help---
		Enable RS-485 interface on UART7. Your board config will have to
		provide GPIO_UART7_RS485_DIR pin definition. Currently it cannot be
		used with UART7_RXDMA.

config UART7_RS485_DIR_POLARITY
	int "UART7 RS-485 DIR pin polarity"
	default 1
	range 0 1
	depends on UART7_RS485
	---help---
		Polarity of DIR pin for RS-485 on UART7. Set to state on DIR pin which
		enables TX (0 - low / nTXEN, 1 - high / TXEN).

config UART7_RXDMA
	bool "UART7 RX DMA"
	default n
	depends on STM32H5_UART7 && (STM32H5_DMA1 || STM32H5_DMA2)
	---help---
		In high data rate usage, Rx DMA may eliminate Rx overrun errors

endif # UART7_SERIALDRIVER

if UART8_SERIALDRIVER

config UART8_RS485
	bool "RS-485 on UART8"
	default n
	depends on STM32H5_UART8
	---help---
		Enable RS-485 interface on UART8. Your board config will have to
		provide GPIO_UART8_RS485_DIR pin definition. Currently it cannot be
		used with UART8_RXDMA.

config UART8_RS485_DIR_POLARITY
	int "UART8 RS-485 DIR pin polarity"
	default 1
	range 0 1
	depends on UART8_RS485
	---help---
		Polarity of DIR pin for RS-485 on UART8. Set to state on DIR pin which
		enables TX (0 - low / nTXEN, 1 - high / TXEN).

config UART8_RXDMA
	bool "UART8 RX DMA"
	default n
	depends on STM32H5_UART8 && (STM32H5_DMA1 || STM32H5_DMA2)
	---help---
		In high data rate usage, Rx DMA may eliminate Rx overrun errors

endif # UART8_SERIALDRIVER

if UART9_SERIALDRIVER

config UART9_RS485
	bool "RS-485 on UART9"
	default n
	depends on STM32H5_UART9
	---help---
		Enable RS-485 interface on UART9. Your board config will have to
		provide GPIO_UART9_RS485_DIR pin definition. Currently it cannot be
		used with UART9_RXDMA.

config UART9_RS485_DIR_POLARITY
	int "UART9 RS-485 DIR pin polarity"
	default 1
	range 0 1
	depends on UART9_RS485
	---help---
		Polarity of DIR pin for RS-485 on UART9. Set to state on DIR pin which
		enables TX (0 - low / nTXEN, 1 - high / TXEN).

config UART9_RXDMA
	bool "UART9 RX DMA"
	default n
	depends on STM32H5_UART9 && (STM32H5_DMA1 || STM32H5_DMA2)
	---help---
		In high data rate usage, Rx DMA may eliminate Rx overrun errors

endif # UART9_SERIALDRIVER

if USART10_SERIALDRIVER

config USART10_RS485
	bool "RS-485 on USART10"
	default n
	depends on STM32H5_USART10
	---help---
		Enable RS-485 interface on USART10. Your board config will have to
		provide GPIO_USART10_RS485_DIR pin definition. Currently it cannot be
		used with USART10_RXDMA.

config USART10_RS485_DIR_POLARITY
	int "USART10 RS-485 DIR pin polarity"
	default 1
	range 0 1
	depends on USART10_RS485
	---help---
		Polarity of DIR pin for RS-485 on USART10. Set to state on DIR pin which
		enables TX (0 - low / nTXEN, 1 - high / TXEN).

config USART10_RXDMA
	bool "USART10 RX DMA"
	default n
	depends on STM32H5_USART10 && (STM32H5_DMA1 || STM32H5_DMA2)
	---help---
		In high data rate usage, Rx DMA may eliminate Rx overrun errors

endif # USART10_SERIALDRIVER

if USART11_SERIALDRIVER

config USART11_RS485
	bool "RS-485 on USART11"
	default n
	depends on STM32H5_USART11
	---help---
		Enable RS-485 interface on USART11. Your board config will have to
		provide GPIO_USART11_RS485_DIR pin definition. Currently it cannot be
		used with USART11_RXDMA.

config USART11_RS485_DIR_POLARITY
	int "USART11 RS-485 DIR pin polarity"
	default 1
	range 0 1
	depends on USART11_RS485
	---help---
		Polarity of DIR pin for RS-485 on USART11. Set to state on DIR pin which
		enables TX (0 - low / nTXEN, 1 - high / TXEN).

config USART11_RXDMA
	bool "USART11 RX DMA"
	default n
	depends on STM32H5_USART11 && (STM32H5_DMA1 || STM32H5_DMA2)
	---help---
		In high data rate usage, Rx DMA may eliminate Rx overrun errors

endif # USART11_SERIALDRIVER

if UART12_SERIALDRIVER

config UART12_RS485
	bool "RS-485 on UART12"
	default n
	depends on STM32H5_UART12
	---help---
		Enable RS-485 interface on UART12. Your board config will have to
		provide GPIO_UART12_RS485_DIR pin definition. Currently it cannot be
		used with UART12_RXDMA.

config UART12_RS485_DIR_POLARITY
	int "UART12 RS-485 DIR pin polarity"
	default 1
	range 0 1
	depends on UART12_RS485
	---help---
		Polarity of DIR pin for RS-485 on UART12. Set to state on DIR pin which
		enables TX (0 - low / nTXEN, 1 - high / TXEN).

config UART12_RXDMA
	bool "UART12 RX DMA"
	default n
	depends on STM32H5_UART12 && (STM32H5_DMA1 || STM32H5_DMA2)
	---help---
		In high data rate usage, Rx DMA may eliminate Rx overrun errors

endif # UART12_SERIALDRIVER

if STM32H5_SERIALDRIVER

comment "Serial Driver Configuration"

config STM32H5_SERIAL_RXDMA_BUFFER_SIZE
	int "Rx DMA buffer size"
	default 32
	depends on USART1_RXDMA || USART2_RXDMA || USART3_RXDMA || USART6_RXDMA || USART10_RXDMA || \
		   USART11_RXDMA || UART4_RXDMA || UART5_RXDMA || UART7_RXDMA || UART8_RXDMA || \
		   UART9_RXDMA || UART12_RXDMA || LPUART1_RXDMA
	---help---
		The DMA buffer size when using RX DMA to emulate a FIFO.

		When streaming data, the generic serial layer will be called
		every time the FIFO receives half this number of bytes.

		Value given here will be rounded up to next multiple of 32 bytes.

config STM32H5_SERIAL_DISABLE_REORDERING
	bool "Disable reordering of ttySx devices."
	depends on STM32H5_USART1 || STM32H5_USART2 || STM32H5_USART3 || STM32H5_UART4 || STM32H5_UART5
	default n
	---help---
		NuttX per default reorders the serial ports (/dev/ttySx) so that the
		console is always on /dev/ttyS0. If more than one UART is in use this
		can, however, have the side-effect that all port mappings
		(hardware USART1 -> /dev/ttyS0) change if the console is moved to another
		UART. This is in particular relevant if a project uses the USB console
		in some boards and a serial console in other boards, but does not
		want the side effect of having all serial port names change when just
		the console is moved from serial to USB.

config STM32H5_FLOWCONTROL_BROKEN
	bool "Use Software UART RTS flow control"
	depends on STM32H5_USART
	default n
	---help---
		Enable UART RTS flow control using Software. Because STM
		Current STM32 have broken HW based RTS behavior (they assert
		nRTS after every byte received)  Enable this setting workaround
		this issue by using software based management of RTS

config STM32H5_USART_BREAKS
	bool "Add TIOxSBRK to support sending Breaks"
	depends on STM32H5_USART
	default n
	---help---
		Add TIOCxBRK routines to send a line break per the STM32 manual, the
		break will be a pulse based on the value M. This is not a BSD compatible
		break.

config STM32H5_SERIALBRK_BSDCOMPAT
	bool "Use GPIO To send Break"
	depends on STM32H5_USART && STM32H5_USART_BREAKS
	default n
	---help---
		Enable using GPIO on the TX pin to send a BSD compatible break:
		TIOCSBRK will start the break and TIOCCBRK will end the break.
		The current STM32H5 U[S]ARTS have no way to leave the break on
		(TX=LOW) because software starts the break and then the hardware
		automatically clears the break. This makes it difficult to send
		a long break.

config STM32H5_USART_SINGLEWIRE
	bool "Single Wire Support"
	default n
	depends on STM32H5_USART
	---help---
		Enable single wire UART support.  The option enables support for the
		TIOCSSINGLEWIRE ioctl in the STM32H5 serial driver.

config STM32H5_USART_INVERT
	bool "Signal Invert Support"
	default n
	depends on STM32H5_USART
	---help---
		Enable signal inversion UART support. The option enables support for the
		TIOCSINVERT ioctl in the STM32H5 serial driver.

config STM32H5_USART_SWAP
	bool "Swap RX/TX pins support"
	default n
	depends on STM32H5_USART
	---help---
		Enable RX/TX pin swapping support. The option enables support for the
		TIOCSSWAP ioctl in the STM32H5 serial driver.

if PM

config STM32H5_PM_SERIAL_ACTIVITY
	int "PM serial activity"
	default 10
	---help---
		PM activity reported to power management logic on every serial
		interrupt.

endif
endif # STM32H5_SERIALDRIVER

endmenu # U[S]ART Configuration

menu "Ethernet MAC Configuration"
	depends on STM32H5_ETHMAC

config STM32H5_PHYADDR
	int "PHY address"
	default 0
	---help---
		The 5-bit address of the PHY on the board. Default: 0

config STM32H5_PHYINIT
	bool "Board-specific PHY Initialization"
	default n
	---help---
		Some boards require specialized initialization of the PHY before it can be used.
		This may include such things as configuring GPIOs, resetting the PHY, etc.
		If STM32H5_PHYINIT is defined in the configuration then the board specific logic
		must provide stm32_phyinitialize(); The STM32 Ethernet driver will call this
		function one time before it first uses the PHY.

config STM32H5_PHY_POLLING
	bool "Support network monitoring by polling the PHY"
	default n
	depends on STM32H5_HAVE_PHY_POLLED
	select ARCH_PHY_POLLED
	---help---
		Some boards may not have an interrupt connected to the PHY.
		This option allows the network monitor to be used by polling the PHY for status.

config STM32H5_MII
	bool "Use MII interface"
	default n
	---help---
		Support Ethernet MII interface.

choice
	prompt "MII clock configuration"
	default STM32H5_MII_EXTCLK
	depends on STM32H5_MII

config STM32H5_MII_MCO1
	bool "Use MC01 as MII clock"
	---help---
		Use MC01 to clock the MII interface.

config STM32H5_MII_MCO2
	bool "Use MC02 as MII clock"
	---help---
		Use MC02 to clock the MII interface.

config STM32H5_MII_EXTCLK
	bool "External MII clock"
	---help---
		Clocking is provided by external logic.

endchoice

config STM32H5_AUTONEG
	bool "Use autonegotiation"
	default y
	---help---
		Use PHY autonegotiation to determine speed and mode

config STM32H5_ETH_NRXDESC
	int "Number of RX descriptors"
	default 8
	---help---
		Number of RX DMA descriptors to use.

config STM32H5_ETH_NTXDESC
	int "Number of TX descriptors"
	default 4
	---help---
		Number of TX DMA descriptors to use.

config STM32H5_ETHFD
	bool "Full duplex"
	default n
	depends on !STM32H5_AUTONEG
	---help---
		If STM32H5_AUTONEG is not defined, then this may be defined to select full duplex
		mode. Default: half-duplex

config STM32H5_ETH100MBPS
	bool "100 Mbps"
	default n
	depends on !STM32H5_AUTONEG
	---help---
		If STM32H5_AUTONEG is not defined, then this may be defined to select 100 MBps
		speed.  Default: 10 Mbps

config STM32H5_PHYSR
	int "PHY Status Register Address (decimal)"
	depends on STM32H5_AUTONEG
	---help---
		This must be provided if STM32H5_AUTONEG is defined.  The PHY status register
		address may diff from PHY to PHY.  This configuration sets the address of
		the PHY status register.

config STM32H5_PHYSR_ALTCONFIG
	bool "PHY Status Alternate Bit Layout"
	default n
	depends on STM32H5_AUTONEG
	---help---
		Different PHYs present speed and mode information in different ways.  Some
		will present separate information for speed and mode (this is the default).
		Those PHYs, for example, may provide a 10/100 Mbps indication and a separate
		full/half duplex indication. This options selects an alternative representation
		where speed and mode information are combined.  This might mean, for example,
		separate bits for 10HD, 100HD, 10FD and 100FD.

config STM32H5_PHYSR_SPEED
	hex "PHY Speed Mask"
	depends on STM32H5_AUTONEG && !STM32H5_PHYSR_ALTCONFIG
	---help---
		This must be provided if STM32H5_AUTONEG is defined.  This provides bit mask
		for isolating the 10 or 100MBps speed indication.

config STM32H5_PHYSR_100MBPS
	hex "PHY 100Mbps Speed Value"
	depends on STM32H5_AUTONEG && !STM32H5_PHYSR_ALTCONFIG
	---help---
		This must be provided if STM32H5_AUTONEG is defined.  This provides the value
		of the speed bit(s) indicating 100MBps speed.

config STM32H5_PHYSR_MODE
	hex "PHY Mode Mask"
	depends on STM32H5_AUTONEG && !STM32H5_PHYSR_ALTCONFIG
	---help---
		This must be provided if STM32H5_AUTONEG is defined.  This provide bit mask
		for isolating the full or half duplex mode bits.

config STM32H5_PHYSR_FULLDUPLEX
	hex "PHY Full Duplex Mode Value"
	depends on STM32H5_AUTONEG && !STM32H5_PHYSR_ALTCONFIG
	---help---
		This must be provided if STM32H5_AUTONEG is defined.  This provides the
		value of the mode bits indicating full duplex mode.

config STM32H5_PHYSR_ALTMODE
	hex "PHY Mode Mask"
	depends on STM32H5_AUTONEG && STM32H5_PHYSR_ALTCONFIG
	---help---
		This must be provided if STM32H5_AUTONEG is defined.  This provide bit mask
		for isolating the speed and full/half duplex mode bits.

config STM32H5_PHYSR_10HD
	hex "10MBase-T Half Duplex Value"
	depends on STM32H5_AUTONEG && STM32H5_PHYSR_ALTCONFIG
	---help---
		This must be provided if STM32H5_AUTONEG is defined.  This is the value
		under the bit mask that represents the 10Mbps, half duplex setting.

config STM32H5_PHYSR_100HD
	hex "100Base-T Half Duplex Value"
	depends on STM32H5_AUTONEG && STM32H5_PHYSR_ALTCONFIG
	---help---
		This must be provided if STM32H5_AUTONEG is defined.  This is the value
		under the bit mask that represents the 100Mbps, half duplex setting.

config STM32H5_PHYSR_10FD
	hex "10Base-T Full Duplex Value"
	depends on STM32H5_AUTONEG && STM32H5_PHYSR_ALTCONFIG
	---help---
		This must be provided if STM32H5_AUTONEG is defined.  This is the value
		under the bit mask that represents the 10Mbps, full duplex setting.

config STM32H5_PHYSR_100FD
	hex "100Base-T Full Duplex Value"
	depends on STM32H5_AUTONEG && STM32H5_PHYSR_ALTCONFIG
	---help---
		This must be provided if STM32H5_AUTONEG is defined.  This is the value
		under the bit mask that represents the 100Mbps, full duplex setting.

config STM32H5_ETH_PTP
	bool "Precision Time Protocol (PTP)"
	default n
	---help---
		Precision Time Protocol (PTP).  Not supported but some hooks are indicated
		with this condition.

config STM32H5_RMII
	bool
	default !STM32H5_MII

choice
	prompt "RMII clock configuration"
	default STM32H5_RMII_EXTCLK
	depends on STM32H5_RMII

config STM32H5_RMII_MCO1
	bool "Use MC01 as RMII clock"
	---help---
		Use MCO1 to clock the RMII interface.

config STM32H5_RMII_MCO2
	bool "Use MC02 as RMII clock"
	---help---
		Use MCO2 to clock the RMII interface.

config STM32H5_RMII_EXTCLK
	bool "External RMII clock"
	---help---
		Clocking is provided by external logic.

endchoice # RMII clock configuration

config STM32H5_ETHMAC_REGDEBUG
	bool "Register-Level Debug"
	default n
	depends on DEBUG_NET_INFO
	---help---
		Enable very low-level register access debug.  Depends on
		CONFIG_DEBUG_FEATURES.

config STM32H5_NO_PHY
	bool "MAC has no PHY"
	default n

endmenu # Ethernet MAC Configuration

menu "FDCAN driver configuration"
	depends on STM32H5_FDCAN

choice
	prompt "FDCAN character driver or SocketCAN support"
	default STM32H5_FDCAN_CHARDRIVER

config STM32H5_FDCAN_CHARDRIVER
	bool "STM32 FDCAN character driver support"
	select ARCH_HAVE_CAN_ERRORS
	select CAN

config STM32H5_FDCAN_SOCKET
	bool "STM32 FDCAN SocketCAN support"
	select NET_CAN_HAVE_ERRORS
	select NET_CAN_HAVE_CANFD

endchoice # FDCAN character driver or SocketCAN support

config STM32H5_FDCAN_REGDEBUG
	bool "CAN Register level debug"
	depends on DEBUG_CAN_INFO
	default n
	---help---
		Output detailed register-level CAN device debug information.
		Requires also CONFIG_DEBUG_CAN_INFO.

config STM32H5_FDCAN_QUEUE_MODE
	bool "FDCAN QUEUE mode (vs FIFO mode)"
	default n

menu "FDCAN1 device driver options"
	depends on STM32H5_FDCAN1

choice
	prompt "FDCAN1 frame format"
	default STM32H5_FDCAN1_ISO11898_1

config STM32H5_FDCAN1_ISO11898_1
	bool "ISO11898-1"
	---help---
		Enable ISO11898-1 frame format

config STM32H5_FDCAN1_NONISO_FORMAT
	bool "Non ISO"
	---help---
		Enable Non ISO, Bosch CAN FD Specification V1.0

endchoice # FDCAN1 frame format

choice
	prompt "FDCAN1 mode"
	default STM32H5_FDCAN1_CLASSIC

config STM32H5_FDCAN1_CLASSIC
	bool "Classic CAN"
	---help---
		Enable Classic CAN mode

config STM32H5_FDCAN1_FD
	bool "CAN FD"
	depends on CAN_FD || NET_CAN_CANFD
	---help---
		Enable CAN FD mode

config STM32H5_FDCAN1_FD_BRS
	bool "CAN FD with fast bit rate switching"
	depends on CAN_FD || NET_CAN_CANFD
	---help---
		Enable CAN FD mode with fast bit rate switching mode.

endchoice # FDCAN1 mode

menu "FDCAN1 Bit Timing"

config STM32H5_FDCAN1_AUTO_BIT_TIMING
	bool "FDCAN1 Automatic Bit Timing"
	default y
	---help---
		Automatically determine FDCAN1 bit timing (nominal and data) based on bitrate.

comment "Nominal Bit Timing"

config STM32H5_FDCAN1_BITRATE
	int "FDCAN bitrate"
	default 500000
	range 0 1000000
	---help---
		FDCAN1 bitrate in bits per second.  Required if STM32H5_FDCAN1 is defined.

config STM32H5_FDCAN1_NTSEG1
	int "FDCAN1 NTSEG1 (PropSeg + PhaseSeg1)"
	default 6
	range 1 256
	depends on !STM32H5_FDCAN1_AUTO_BIT_TIMING
	---help---
		The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2).

config STM32H5_FDCAN1_NTSEG2
	int "FDCAN1 NTSEG2 (PhaseSeg2)"
	default 7
	range 1 128
	depends on !STM32H5_FDCAN1_AUTO_BIT_TIMING
	---help---
		The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2).

config STM32H5_FDCAN1_NSJW
	int "FDCAN1 synchronization jump width"
	default 1
	range 1 128
	depends on !STM32H5_FDCAN1_AUTO_BIT_TIMING
	---help---
		The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2).

comment "Data Bit Timing"
	depends on CAN_FD && STM32H5_FDCAN1_FD_BRS

config STM32H5_FDCAN1_DBITRATE
	int "FDCAN1 data bitrate"
	default 2000000
	depends on CAN_FD && STM32H5_FDCAN1_FD_BRS
	---help---
		FDCAN1 bitrate in bits per second.  Required if operating in FD mode with bit rate switching (BRS).

config STM32H5_FDCAN1_DTSEG1
	int "FDCAN1 DTSEG1 (PropSeg + PhaseSeg1 of data phase)"
	default 4
	range 1 31
	depends on CAN_FD && STM32H5_FDCAN1_FD_BRS && !STM32H5_FDCAN1_AUTO_BIT_TIMING
	---help---
		The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2).

config STM32H5_FDCAN1_DTSEG2
	int "FDCAN1 DTSEG2 (PhaseSeg2 of data phase)"
	default 4
	range 1 15
	depends on CAN_FD && STM32H5_FDCAN1_FD_BRS && !STM32H5_FDCAN1_AUTO_BIT_TIMING
	---help---
		The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2).

config STM32H5_FDCAN1_DSJW
	int "FDCAN1 fast synchronization jump width"
	default 2
	range 1 15
	depends on CAN_FD && STM32H5_FDCAN1_FD_BRS && !STM32H5_FDCAN1_AUTO_BIT_TIMING
	---help---
		The duration of a synchronization jump is Tcan_clk x DSJW.

endmenu # FDCAN1 Bit Timing

config STM32H5_FDCAN1_LOOPBACK
	bool "Enable FDCAN1 loopback mode"
	default n
	---help---
		Enable the FDCAN1 local loopback mode for testing purposes.

endmenu # FDCAN1 device driver options

menu "FDCAN2 device driver options"
	depends on STM32H5_FDCAN2

choice
	prompt "FDCAN2 frame format"
	default STM32H5_FDCAN2_ISO11898_1

config STM32H5_FDCAN2_ISO11898_1
	bool "ISO11898-1"
	---help---
		Enable ISO11898-1 frame format

config STM32H5_FDCAN2_NONISO_FORMAT
	bool "Non ISO"
	---help---
		Enable Non ISO, Bosch CAN FD Specification V1.0

endchoice # FDCAN2 frame format

choice
	prompt "FDCAN2 mode"
	default STM32H5_FDCAN2_CLASSIC

config STM32H5_FDCAN2_CLASSIC
	bool "Classic CAN"
	---help---
		Enable Classic CAN mode

config STM32H5_FDCAN2_FD
	bool "CAN FD"
	depends on CAN_FD || NET_CAN_CANFD
	---help---
		Enable CAN FD mode

config STM32H5_FDCAN2_FD_BRS
	bool "CAN FD with fast bit rate switching"
	depends on CAN_FD || NET_CAN_CANFD
	---help---
		Enable CAN FD mode with fast bit rate switching mode.

endchoice # FDCAN2 mode

menu "FDCAN2 Bit Timing"

config STM32H5_FDCAN2_AUTO_BIT_TIMING
	bool "FDCAN2 Automatic Bit Timing"
	default y
	---help---
		Automatically determine FDCAN2 bit timing (nominal and data) based on bitrate.

comment "Nominal Bit Timing"

config STM32H5_FDCAN2_BITRATE
	int "FDCAN bitrate"
	default 500000
	range 0 1000000
	---help---
		FDCAN2 bitrate in bits per second.  Required if STM32H5_FDCAN2 is defined.

config STM32H5_FDCAN2_NTSEG1
	int "FDCAN2 NTSEG1 (PropSeg + PhaseSeg1)"
	default 6
	range 1 256
	depends on !STM32H5_FDCAN2_AUTO_BIT_TIMING
	---help---
		The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2).

config STM32H5_FDCAN2_NTSEG2
	int "FDCAN2 NTSEG2 (PhaseSeg2)"
	default 7
	range 1 128
	depends on !STM32H5_FDCAN2_AUTO_BIT_TIMING
	---help---
		The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2).

config STM32H5_FDCAN2_NSJW
	int "FDCAN2 synchronization jump width"
	default 1
	range 1 128
	depends on !STM32H5_FDCAN2_AUTO_BIT_TIMING
	---help---
		The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2).

comment "Data Bit Timing"
	depends on CAN_FD && STM32H5_FDCAN2_FD_BRS

config STM32H5_FDCAN2_DBITRATE
	int "FDCAN2 data bitrate"
	default 2000000
	depends on CAN_FD && STM32H5_FDCAN2_FD_BRS
	---help---
		FDCAN2 bitrate in bits per second.  Required if operating in FD mode with bit rate switching (BRS).

config STM32H5_FDCAN2_DTSEG1
	int "FDCAN2 DTSEG1 (PropSeg + PhaseSeg1 of data phase)"
	default 4
	range 1 31
	depends on CAN_FD && STM32H5_FDCAN2_FD_BRS && !STM32H5_FDCAN2_AUTO_BIT_TIMING
	---help---
		The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2).

config STM32H5_FDCAN2_DTSEG2
	int "FDCAN2 DTSEG2 (PhaseSeg2 of data phase)"
	default 4
	range 1 15
	depends on CAN_FD && STM32H5_FDCAN2_FD_BRS && !STM32H5_FDCAN2_AUTO_BIT_TIMING
	---help---
		The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2).

config STM32H5_FDCAN2_DSJW
	int "FDCAN2 fast synchronization jump width"
	default 2
	range 1 15
	depends on CAN_FD && STM32H5_FDCAN2_FD_BRS && !STM32H5_FDCAN2_AUTO_BIT_TIMING
	---help---
		The duration of a synchronization jump is Tcan_clk x DSJW.

endmenu # FDCAN2 Bit Timing

config STM32H5_FDCAN2_LOOPBACK
	bool "Enable FDCAN2 loopback mode"
	default n
	---help---
		Enable the FDCAN2 local loopback mode for testing purposes.

endmenu # FDCAN2 device driver options

endmenu # "FDCAN driver configuration"

menu "I2C Configuration"
	depends on STM32H5_I2C

menu "Clock Selection"

choice
	depends on STM32H5_I2C1
	prompt "I2C1 Input Clock Selection"
	default STM32H5_I2C1_CLK_PCLK1

config STM32H5_I2C1_CLK_CSI
	bool "CSI"

config STM32H5_I2C1_CLK_HSI
	bool "HSI"

config STM32H5_I2C1_CLK_PCLK1
	bool "PCLK1"

config STM32H5_I2C1_CLK_PLL3R
	bool "PLL3R"

endchoice # I2C1 Input Clock Selection

choice
	depends on STM32H5_I2C2
	prompt "I2C2 Input Clock Selection"
	default STM32H5_I2C2_CLK_PCLK1

config STM32H5_I2C2_CLK_CSI
	bool "CSI"

config STM32H5_I2C2_CLK_HSI
	bool "HSI"

config STM32H5_I2C2_CLK_PCLK1
	bool "PCLK1"

config STM32H5_I2C2_CLK_PLL3R
	bool "PLL3R"

endchoice # I2C2 Input Clock Selection

choice
	depends on STM32H5_I2C3
	prompt "I2C3 Input Clock Selection"
	default STM32H5_I2C3_CLK_PCLK3

config STM32H5_I2C3_CLK_CSI
	bool "CSI"

config STM32H5_I2C3_CLK_HSI
	bool "HSI"

config STM32H5_I2C3_CLK_PCLK3
	bool "PCLK3"

config STM32H5_I2C3_CLK_PLL3R
	bool "PLL3R"

endchoice # I2C3 Input Clock Selection

choice
	depends on STM32H5_I2C4
	prompt "I2C4 Input Clock Selection"
	default STM32H5_I2C4_CLK_PCLK3

config STM32H5_I2C4_CLK_CSI
	bool "CSI"

config STM32H5_I2C4_CLK_HSI
	bool "HSI"

config STM32H5_I2C4_CLK_PCLK3
	bool "PCLK3"

config STM32H5_I2C4_CLK_PLL3R
	bool "PLL3R"

endchoice # I2C4 Input Clock Selection

endmenu # Clock Selection

menu "Rise/Fall Override"

config STM32H5_I2C1_RF_OVERRIDE
	bool "I2C1"
	default n
	depends on STM32H5_I2C1

config STM32H5_I2C2_RF_OVERRIDE
	bool "I2C2"
	default n
	depends on STM32H5_I2C2

config STM32H5_I2C3_RF_OVERRIDE
	bool "I2C3"
	default n
	depends on STM32H5_I2C3

config STM32H5_I2C4_RF_OVERRIDE
	bool "I2C4"
	default n
	depends on STM32H5_I2C4

menu "Rise/Fall Values"

config STM32H5_I2C1_RISE
	int "I2C1 Rise Time (ns)"
	range 0 1000
	default 20
	depends on STM32H5_I2C1_RF_OVERRIDE

config STM32H5_I2C1_FALL
	int "I2C1 Fall Time (ns)"
	range 0 300
	default 20
	depends on STM32H5_I2C1_RF_OVERRIDE

config STM32H5_I2C2_RISE
	int "I2C2 Rise Time (ns)"
	range 0 1000
	default 20
	depends on STM32H5_I2C2_RF_OVERRIDE

config STM32H5_I2C2_FALL
	int "I2C2 Fall Time (ns)"
	range 0 300
	default 20
	depends on STM32H5_I2C2_RF_OVERRIDE

config STM32H5_I2C3_RISE
	int "I2C3 Rise Time (ns)"
	range 0 1000
	default 20
	depends on STM32H5_I2C3_RF_OVERRIDE

config STM32H5_I2C3_FALL
	int "I2C3 Fall Time (ns)"
	range 0 300
	default 20
	depends on STM32H5_I2C3_RF_OVERRIDE

config STM32H5_I2C4_RISE
	int "I2C4 Rise Time (ns)"
	range 0 1000
	default 20
	depends on STM32H5_I2C4_RF_OVERRIDE

config STM32H5_I2C4_FALL
	int "I2C4 Fall Time (ns)"
	range 0 300
	default 20
	depends on STM32H5_I2C4_RF_OVERRIDE

endmenu # Rise/Fall Values

endmenu # Rise/Fall Override

menu "Filtering"

menu "Digital Filters"

config STM32H5_I2C1_DNF
	int "I2C1 Digital Noise Filter"
	range 0 15
	default 0
	depends on STM32H5_I2C1

config STM32H5_I2C2_DNF
	int "I2C2 Digital Noise Filter"
	range 0 15
	default 0
	depends on STM32H5_I2C2

config STM32H5_I2C3_DNF
	int "I2C3 Digital Noise Filter"
	range 0 15
	default 0
	depends on STM32H5_I2C3

config STM32H5_I2C4_DNF
	int "I2C4 Digital Noise Filter"
	range 0 15
	default 0
	depends on STM32H5_I2C4

endmenu # Digital Filters

menu "Analog Filters"

config STM32H5_I2C1_ANFOFF
	int "Turn off I2C1 Analog Filter (0=on, 1=off)"
	default 1
	range 0 1
	depends on STM32H5_I2C1

config STM32H5_I2C2_ANFOFF
	int "Turn off I2C2 Analog Filter (0=on, 1=off)"
	default 1
	range 0 1
	depends on STM32H5_I2C2

config STM32H5_I2C3_ANFOFF
	int "Turn off I2C3 Analog Filter (0=on, 1=off)"
	default 1
	range 0 1
	depends on STM32H5_I2C3

config STM32H5_I2C4_ANFOFF
	int "Turn off I2C4 Analog Filter (0=on, 1=off)"
	default 1
	range 0 1
	depends on STM32H5_I2C4

endmenu # Analog Filters

endmenu # Filtering

config STM32H5_I2C_DYNTIMEO
	bool "Use dynamic timeouts"
	default n
	depends on STM32H5_I2C

config STM32H5_I2C_DYNTIMEO_USECPERBYTE
	int "Timeout Microseconds per Byte"
	default 500
	depends on STM32H5_I2C_DYNTIMEO

config STM32H5_I2C_DYNTIMEO_STARTSTOP
	int "Timeout for Start/Stop (Milliseconds)"
	default 1000
	depends on STM32H5_I2C_DYNTIMEO

config STM32H5_I2CTIMEOSEC
	int "Timeout seconds"
	default 0
	depends on STM32H5_I2C

config STM32H5_I2CTIMEOMS
	int "Timeout Milliseconds"
	default 500
	depends on STM32H5_I2C && !STM32H5_I2C_DYNTIMEO

config STM32H5_I2CTIMEOTICKS
	int "Timeout for Done and Stop (ticks)"
	default 500
	depends on STM32H5_I2C && !STM32H5_I2C_DYNTIMEO

endmenu # "I2C Configuration"

menu "QuadSPI Configuration"
	depends on STM32H5_QSPI1

config STM32H5_QSPI_FLASH_SIZE
	int "Size of attached serial flash, bytes"
	default 16777216
	range 1 2147483648
	---help---
		The STM32H5 QSPI peripheral requires the size of the Flash be specified

config STM32H5_QSPI_FIFO_THESHOLD
	int "Number of bytes before asserting FIFO threshold flag"
	default 4
	range 1 32
	---help---
		The STM32H5 QSPI peripheral requires that the FIFO threshold be specified
		I would leave it at the default value of 4 unless you know what you are doing.

config STM32H5_QSPI_CSHT
	int "Number of cycles Chip Select must be inactive between transactions"
	default 5
	range 1 64
	---help---
		The STM32H5 QSPI peripheral requires that it be specified the minimum number
		of AHB cycles that Chip Select be held inactive between transactions.

choice
	prompt "Transfer technique"
	default STM32H5_QSPI_DMA
	---help---
		You can choose between using polling, interrupts, or DMA to transfer data
		over the QSPI interface.

config STM32H5_QSPI_POLLING
	bool "Polling"
	---help---
		Use conventional register I/O with status polling to transfer data.

config STM32H5_QSPI_INTERRUPTS
	bool "Interrupts"
	---help---
		User interrupt driven I/O transfers.

config STM32H5_QSPI_DMA
	bool "DMA"
	depends on STM32H5_DMA
	---help---
		Use DMA to improve QSPI transfer performance.

endchoice

choice
	prompt "Bank selection"
	default STM32H5_QSPI_MODE_BANK1
	---help---
		You can choose between using polling, interrupts, or DMA to transfer data
		over the QSPI interface.

config STM32H5_QSPI_MODE_BANK1
	bool "Bank 1"

config STM32H5_QSPI_MODE_BANK2
	bool "Bank 2"

config STM32H5_QSPI_MODE_DUAL
	bool "Dual Bank"

endchoice

choice
	prompt "DMA Priority"
	default STM32H5_QSPI_DMAPRIORITY_MEDIUM
	depends on STM32H5_DMA
	---help---
		The DMA controller supports priority levels.  You are probably fine
		with the default of 'medium' except for special cases.  In the event
		of contention between to channels at the same priority, the lower
		numbered channel has hardware priority over the higher numbered one.

config STM32H5_QSPI_DMAPRIORITY_VERYHIGH
	bool "Very High priority"
	depends on STM32H5_DMA
	---help---
		'Highest' priority.

config STM32H5_QSPI_DMAPRIORITY_HIGH
	bool "High priority"
	depends on STM32H5_DMA
	---help---
		'High' priority.

config STM32H5_QSPI_DMAPRIORITY_MEDIUM
	bool "Medium priority"
	depends on STM32H5_DMA
	---help---
		'Medium' priority.

config STM32H5_QSPI_DMAPRIORITY_LOW
	bool "Low priority"
	depends on STM32H5_DMA
	---help---
		'Low' priority.

endchoice

config STM32H5_QSPI_DMATHRESHOLD
	int "QSPI DMA threshold"
	default 4
	depends on STM32H5_QSPI_DMA
	---help---
		When QSPI DMA is enabled, small DMA transfers will still be performed
		by polling logic.  This value is the threshold below which transfers
		will still be performed by conventional register status polling.

config STM32H5_QSPI_DMADEBUG
	bool "QSPI DMA transfer debug"
	depends on STM32H5_QSPI_DMA && DEBUG_SPI && DEBUG_DMA
	default n
	---help---
		Enable special debug instrumentation to analyze QSPI DMA data transfers.
		This logic is as non-invasive as possible:  It samples DMA
		registers at key points in the data transfer and then dumps all of
		the registers at the end of the transfer.

config STM32H5_QSPI_REGDEBUG
	bool "QSPI Register level debug"
	depends on DEBUG_SPI_INFO
	default n
	---help---
		Output detailed register-level QSPI device debug information.
		Requires also CONFIG_DEBUG_SPI_INFO.

endmenu

endif # ARCH_CHIP_STM32H5
